Attention is currently required from: Tarun Tuli, Sean Rhodes, Subrata Banik, Jonathan Zhang, Johnny Lin, Kapil Porwal, Christian Walter, Arthur Heymans, Tim Chu.
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70044 )
Change subject: sb,soc/intel: Address TCO SECOND_TO_STS name collision ......................................................................
sb,soc/intel: Address TCO SECOND_TO_STS name collision
Later soc/intel/common/smbus addresses TCO2_STS as a separate 16-bit register, while baytrail and braswell assumes 32-bit wide TCO1_STS to extend as TCO2_STS.
In src/soc/intel/denverton_ns: #define TCO2_STS_SECOND_TO 0x02
In soc/intel/baytrail,braswell: #define SECOND_TO_STS (1 << 17)
Elsewehere #define SECOND_TO_STS (1 << 1)
It's expected that we remove the first (1 << 17) case and only access TCO2_STS as a separate 16-bit register. For now, use unique names to avoid confusion.
Change-Id: I07cc46a9d600b2bf2f23588b26891268e9ce4de0 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/intel/alderlake/elog.c M src/soc/intel/apollolake/include/soc/smbus.h M src/soc/intel/baytrail/elog.c M src/soc/intel/baytrail/include/soc/pm.h M src/soc/intel/braswell/elog.c M src/soc/intel/braswell/include/soc/pm.h M src/soc/intel/cannonlake/elog.c M src/soc/intel/common/block/smbus/tco.c M src/soc/intel/common/pch/include/intelpch/smbus.h M src/soc/intel/icelake/elog.c M src/soc/intel/jasperlake/elog.c M src/soc/intel/meteorlake/elog.c M src/soc/intel/skylake/elog.c M src/soc/intel/tigerlake/elog.c M src/soc/intel/xeon_sp/include/soc/smbus.h M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/common/tco.h M src/southbridge/intel/common/watchdog.c M src/southbridge/intel/lynxpoint/elog.c M src/southbridge/intel/lynxpoint/pch.h 20 files changed, 47 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/70044/1
diff --git a/src/soc/intel/alderlake/elog.c b/src/soc/intel/alderlake/elog.c index 7f79d94..b87130f 100644 --- a/src/soc/intel/alderlake/elog.c +++ b/src/soc/intel/alderlake/elog.c @@ -170,7 +170,7 @@
/* TCO Timeout */ if (ps->prev_sleep_state != ACPI_S3 && - ps->tco2_sts & TCO_STS_SECOND_TO) + ps->tco2_sts & TCO2_STS_SECOND_TO) elog_add_event(ELOG_TYPE_TCO_RESET);
/* Power Button Override */ diff --git a/src/soc/intel/apollolake/include/soc/smbus.h b/src/soc/intel/apollolake/include/soc/smbus.h index e11119c..a87211a 100644 --- a/src/soc/intel/apollolake/include/soc/smbus.h +++ b/src/soc/intel/apollolake/include/soc/smbus.h @@ -7,7 +7,7 @@ #define TCO1_STS 0x04 #define TCO_TIMEOUT (1 << 3) #define TCO2_STS 0x06 -#define TCO_STS_SECOND_TO (1 << 1) +#define TCO2_STS_SECOND_TO (1 << 1) #define TCO_INTRD_DET (1 << 0) #define TCO1_CNT 0x08 #define TCO_LOCK (1 << 12) diff --git a/src/soc/intel/baytrail/elog.c b/src/soc/intel/baytrail/elog.c index f732fab..ecdbfca 100644 --- a/src/soc/intel/baytrail/elog.c +++ b/src/soc/intel/baytrail/elog.c @@ -22,7 +22,7 @@ if (ps->gen_pmcon1 & RPS) elog_add_event(ELOG_TYPE_RTC_RESET);
- if (ps->tco_sts & SECOND_TO_STS) + if (ps->tco_sts & TCO1_32_STS_SECOND_TO_STS) elog_add_event(ELOG_TYPE_TCO_RESET);
if (ps->pm1_sts & PRBTNOR_STS) diff --git a/src/soc/intel/baytrail/include/soc/pm.h b/src/soc/intel/baytrail/include/soc/pm.h index 1db5038..5154105 100644 --- a/src/soc/intel/baytrail/include/soc/pm.h +++ b/src/soc/intel/baytrail/include/soc/pm.h @@ -226,7 +226,7 @@ #if CONFIG(TCO_SPACE_NOT_YET_SPLIT) #define TCO_RLD 0x60 #define TCO_STS 0x64 -# define SECOND_TO_STS (1 << 17) +# define TCO1_32_STS_SECOND_TO_STS (1 << 17) # define TCO_TIMEOUT (1 << 3) #define TCO1_CNT 0x68 # define TCO_LOCK (1 << 12) diff --git a/src/soc/intel/braswell/elog.c b/src/soc/intel/braswell/elog.c index f732fab..ecdbfca 100644 --- a/src/soc/intel/braswell/elog.c +++ b/src/soc/intel/braswell/elog.c @@ -22,7 +22,7 @@ if (ps->gen_pmcon1 & RPS) elog_add_event(ELOG_TYPE_RTC_RESET);
- if (ps->tco_sts & SECOND_TO_STS) + if (ps->tco_sts & TCO1_32_STS_SECOND_TO_STS) elog_add_event(ELOG_TYPE_TCO_RESET);
if (ps->pm1_sts & PRBTNOR_STS) diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h index 131a996..b918577 100644 --- a/src/soc/intel/braswell/include/soc/pm.h +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -188,7 +188,7 @@ #if CONFIG(TCO_SPACE_NOT_YET_SPLIT) #define TCO_RLD 0x60 #define TCO_STS 0x64 -# define SECOND_TO_STS (1 << 17) +# define TCO1_32_STS_SECOND_TO_STS (1 << 17) # define TCO_TIMEOUT (1 << 3) #define TCO1_CNT 0x68 # define TCO_LOCK (1 << 12) diff --git a/src/soc/intel/cannonlake/elog.c b/src/soc/intel/cannonlake/elog.c index dcc1a79..f8d0651 100644 --- a/src/soc/intel/cannonlake/elog.c +++ b/src/soc/intel/cannonlake/elog.c @@ -135,7 +135,7 @@
/* TCO Timeout */ if (ps->prev_sleep_state != ACPI_S3 && - ps->tco2_sts & TCO_STS_SECOND_TO) + ps->tco2_sts & TCO2_STS_SECOND_TO) elog_add_event(ELOG_TYPE_TCO_RESET);
/* Power Button Override */ diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c index 1ca8842..12b176c 100644 --- a/src/soc/intel/common/block/smbus/tco.c +++ b/src/soc/intel/common/block/smbus/tco.c @@ -72,7 +72,7 @@
/* TCO Status 2 register */ tco2_sts = tco_read_reg(TCO2_STS); - tco_write_reg(TCO2_STS, tco2_sts | TCO_STS_SECOND_TO); + tco_write_reg(TCO2_STS, tco2_sts | TCO2_STS_SECOND_TO);
return (tco2_sts << 16) | tco1_sts; } diff --git a/src/soc/intel/common/pch/include/intelpch/smbus.h b/src/soc/intel/common/pch/include/intelpch/smbus.h index 238da2b..78b7953 100644 --- a/src/soc/intel/common/pch/include/intelpch/smbus.h +++ b/src/soc/intel/common/pch/include/intelpch/smbus.h @@ -7,7 +7,7 @@ #define TCO1_STS 0x04 #define TCO_TIMEOUT (1 << 3) #define TCO2_STS 0x06 -#define TCO_STS_SECOND_TO (1 << 1) +#define TCO2_STS_SECOND_TO (1 << 1) #define TCO_INTRD_DET (1 << 0) #define TCO1_CNT 0x08 #define TCO_LOCK (1 << 12) diff --git a/src/soc/intel/icelake/elog.c b/src/soc/intel/icelake/elog.c index 4967fde..01f133a 100644 --- a/src/soc/intel/icelake/elog.c +++ b/src/soc/intel/icelake/elog.c @@ -70,7 +70,7 @@
/* TCO Timeout */ if (ps->prev_sleep_state != ACPI_S3 && - ps->tco2_sts & TCO_STS_SECOND_TO) + ps->tco2_sts & TCO2_STS_SECOND_TO) elog_add_event(ELOG_TYPE_TCO_RESET);
/* Power Button Override */ diff --git a/src/soc/intel/jasperlake/elog.c b/src/soc/intel/jasperlake/elog.c index 0e4b2c5..f42e06c 100644 --- a/src/soc/intel/jasperlake/elog.c +++ b/src/soc/intel/jasperlake/elog.c @@ -143,7 +143,7 @@
/* TCO Timeout */ if (ps->prev_sleep_state != ACPI_S3 && - ps->tco2_sts & TCO_STS_SECOND_TO) + ps->tco2_sts & TCO2_STS_SECOND_TO) elog_add_event(ELOG_TYPE_TCO_RESET);
/* Power Button Override */ diff --git a/src/soc/intel/meteorlake/elog.c b/src/soc/intel/meteorlake/elog.c index 35100f9..14d086c 100644 --- a/src/soc/intel/meteorlake/elog.c +++ b/src/soc/intel/meteorlake/elog.c @@ -173,7 +173,7 @@
/* TCO Timeout */ if (ps->prev_sleep_state != ACPI_S3 && - ps->tco2_sts & TCO_STS_SECOND_TO) + ps->tco2_sts & TCO2_STS_SECOND_TO) elog_add_event(ELOG_TYPE_TCO_RESET);
/* Power Button Override */ diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 1761671..325bacb 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -202,7 +202,7 @@
/* TCO Timeout */ if (ps->prev_sleep_state != ACPI_S3 && - ps->tco2_sts & TCO_STS_SECOND_TO) + ps->tco2_sts & TCO2_STS_SECOND_TO) elog_add_event(ELOG_TYPE_TCO_RESET);
/* Power Button Override */ diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c index 29f1712..650d1cd 100644 --- a/src/soc/intel/tigerlake/elog.c +++ b/src/soc/intel/tigerlake/elog.c @@ -178,7 +178,7 @@
/* TCO Timeout */ if (ps->prev_sleep_state != ACPI_S3 && - ps->tco2_sts & TCO_STS_SECOND_TO) + ps->tco2_sts & TCO2_STS_SECOND_TO) elog_add_event(ELOG_TYPE_TCO_RESET);
/* Power Button Override */ diff --git a/src/soc/intel/xeon_sp/include/soc/smbus.h b/src/soc/intel/xeon_sp/include/soc/smbus.h index 00aae2c..7ef9d0b 100644 --- a/src/soc/intel/xeon_sp/include/soc/smbus.h +++ b/src/soc/intel/xeon_sp/include/soc/smbus.h @@ -7,7 +7,7 @@ #define TCO1_STS 0x04 #define TCO_TIMEOUT (1 << 3) #define TCO2_STS 0x06 -#define TCO_STS_SECOND_TO (1 << 1) +#define TCO2_STS_SECOND_TO (1 << 1) #define TCO_INTRD_DET (1 << 0) #define TCO1_CNT 0x08 #define TCO_LOCK (1 << 12) diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index b5e05f6..3aef48a 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -469,7 +469,7 @@ #define TCO1_TIMEOUT (1 << 3) #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 -#define SECOND_TO_STS (1 << 1) +#define TCO2_STS_SECOND_TO (1 << 1) #define TCO1_CNT 0x68 #define TCO_TMR_HLT (1 << 11) #define TCO_LOCK (1 << 12) diff --git a/src/southbridge/intel/common/tco.h b/src/southbridge/intel/common/tco.h index 4c3f639..168971e 100644 --- a/src/southbridge/intel/common/tco.h +++ b/src/southbridge/intel/common/tco.h @@ -15,7 +15,7 @@ #define TCO1_STS 0x04 #define TCO1_TIMEOUT (1 << 3) #define TCO2_STS 0x06 -#define SECOND_TO_STS (1 << 1) +#define TCO2_STS_SECOND_TO (1 << 1) #define TCO1_CNT 0x08 #define TCO_TMR_HLT (1 << 11)
diff --git a/src/southbridge/intel/common/watchdog.c b/src/southbridge/intel/common/watchdog.c index b40c5fe..a988691 100644 --- a/src/southbridge/intel/common/watchdog.c +++ b/src/southbridge/intel/common/watchdog.c @@ -33,7 +33,7 @@
/* Clear TCO timeout status. */ write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_TIMEOUT); - write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, SECOND_TO_STS); + write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, TCO2_STS_SECOND_TO);
printk(BIOS_DEBUG, "ICH-NM10-PCH: watchdog disabled\n"); } diff --git a/src/southbridge/intel/lynxpoint/elog.c b/src/southbridge/intel/lynxpoint/elog.c index 839773a..e73a7ed 100644 --- a/src/southbridge/intel/lynxpoint/elog.c +++ b/src/southbridge/intel/lynxpoint/elog.c @@ -124,7 +124,7 @@ elog_add_event(ELOG_TYPE_PWROK_FAIL);
/* Second TCO Timeout */ - if (tco2_sts & SECOND_TO_STS) + if (tco2_sts & TCO2_STS_SECOND_TO) elog_add_event(ELOG_TYPE_TCO_RESET);
/* Power Button Override */ diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 0d8be7b..35649f6 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -623,7 +623,7 @@ #define TCO1_STS 0x64 #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 -#define SECOND_TO_STS (1 << 1) +#define TCO2_STS_SECOND_TO (1 << 1) #endif
#define ALT_GP_SMI_EN2 0x5c