[coreboot-gerrit] Change in coreboot[master]: sb/intel/i82801gx: Add common LPC decode code

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36700 )

Change subject: sb/intel/i82801gx: Add common LPC decode code
......................................................................

Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/36700/5/src/southbridge/intel/i8280... 
File src/southbridge/intel/i82801gx/early_init.c:

https://review.coreboot.org/c/coreboot/+/36700/5/src/southbridge/intel/i8280... 
PS5, Line 48: 	pci_write_config32(d31f0, GEN1_DEC, config->gen1_dec);
> so by default it writes 0?

Yes. 0 is the reset default and if for some reason it is not that should be written too.