[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Add code for early tcss

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42079 )

Change subject: soc/intel/tigerlake: Add code for early tcss
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Patch Set 22:

(4 comments)

https://review.coreboot.org/c/coreboot/+/42079/22/src/soc/intel/tigerlake/ea... 
File src/soc/intel/tigerlake/early_tcss.c:

https://review.coreboot.org/c/coreboot/+/42079/22/src/soc/intel/tigerlake/ea... 
PS22, Line 59: 	
nit: extra tab here

https://review.coreboot.org/c/coreboot/+/42079/22/src/soc/intel/tigerlake/ea... 
PS22, Line 79: 		res_reg = res->buf[0];
nit: blank line after if block

https://review.coreboot.org/c/coreboot/+/42079/22/src/soc/intel/tigerlake/ea... 
PS22, Line 144: 	cmd = tcss_make_safe_mode_cmd(
              : 		PMC_IPC_TCSS_SAFE_MODE_REQ_RES,
              : 		mux_data.usb3_port);
I think this will all fit on 1 line

https://review.coreboot.org/c/coreboot/+/42079/22/src/soc/intel/tigerlake/ea... 
PS22, Line 179: 	static uint8_t hpd_lvl;
Shouldn't this be a per-port HPD, since the state is stored across calls?