[coreboot-gerrit] Change in coreboot[master]: src/soc/intel/xeon_sp: Fill in the cache information in SMBIOS type 7

[Morgan Jang (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Jonathan Zhang, Johnny Lin, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46119

to look at the new patch set (#6).

Change subject: src/soc/intel/xeon_sp: Fill in the cache information in SMBIOS type 7
......................................................................

src/soc/intel/xeon_sp: Fill in the cache information in SMBIOS type 7

TEST=Execute "dmidecode -t 7" to check if cache error correction type
and cache sram type is correct for each cache level

Change-Id: Ibe7c6ad03a83a6a3b2c7dfcfafaa619e690a418d
Signed-off-by: Morgan Jang 
---
M src/soc/intel/xeon_sp/Makefile.inc
A src/soc/intel/xeon_sp/ramstage.c
2 files changed, 27 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/46119/6