Bruce Griffith (Bruce.Griffith@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3783
-gerrit
commit 7c91c79cb261bdddfd40dc205faa392915341e86 Author: Siyuan Wang wangsiyuanbuaa@gmail.com Date: Tue Jul 9 17:32:42 2013 +0800
AMD Yangtze wrapper for Kabini
AMD Yangtze wrapper uses AMD Hudson wrapper code but has some changes. The changes are necessary and have no effects on Hudson.
Change-Id: Iada90d34fdc2025bd14f566488ee12810a28ac0d Signed-off-by: Siyuan Wang SiYuan.Wang@amd.com Signed-off-by: Siyuan Wang wangsiyuanbuaa@gmail.com Signed-off-by: Bruce Griffith Bruce.Griffith@se-eng.com --- src/include/device/pci_ids.h | 2 ++ src/southbridge/amd/Makefile.inc | 1 + src/southbridge/amd/agesa/Makefile.inc | 1 + src/southbridge/amd/agesa/hudson/Kconfig | 25 ++++++++++++++++++++----- src/southbridge/amd/agesa/hudson/early_setup.c | 3 +++ src/southbridge/amd/agesa/hudson/sata.c | 6 ++++++ src/southbridge/amd/agesa/hudson/sd.c | 20 +++++++++++++++----- src/southbridge/amd/agesa/hudson/sm.c | 1 + src/southbridge/amd/agesa/hudson/spi.c | 9 +++++++++ 9 files changed, 58 insertions(+), 10 deletions(-)
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 5b11e94..f47dc9f 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -363,7 +363,9 @@ #define PCI_DEVICE_ID_ATI_SB900_USB_19_2 0x7808 #define PCI_DEVICE_ID_ATI_SB900_USB_20_5 0x7809 #define PCI_DEVICE_ID_ATI_SB900_GEC 0x7806 + #define PCI_DEVICE_ID_AMD_HUDSON_SD 0x7806 + #define PCI_DEVICE_ID_AMD_YANGTZE_SD 0x7813
#define PCI_DEVICE_ID_ATI_RS690_HT 0x7910 diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc index cce4702..9ec0171 100644 --- a/src/southbridge/amd/Makefile.inc +++ b/src/southbridge/amd/Makefile.inc @@ -15,6 +15,7 @@ subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += agesa +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += agesa
ifeq ($(CONFIG_HAVE_ACPI_RESUME), y) ifeq ($(CONFIG_CPU_AMD_AGESA), y) diff --git a/src/southbridge/amd/agesa/Makefile.inc b/src/southbridge/amd/agesa/Makefile.inc index 822c6fd..fdd5d80 100644 --- a/src/southbridge/amd/agesa/Makefile.inc +++ b/src/southbridge/amd/agesa/Makefile.inc @@ -17,3 +17,4 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += hudson +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += hudson diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index af305ee..5cb1722 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -23,7 +23,13 @@ config SOUTHBRIDGE_AMD_AGESA_HUDSON select HAVE_USBDEBUG select HAVE_HARD_RESET
-if SOUTHBRIDGE_AMD_AGESA_HUDSON +config SOUTHBRIDGE_AMD_AGESA_YANGTZE + bool + select IOAPIC + select HAVE_USBDEBUG + select HAVE_HARD_RESET + +if SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE
config BOOTBLOCK_SOUTHBRIDGE_INIT string @@ -72,17 +78,20 @@ config HUDSON_GEC_FWM
config HUDSON_XHCI_FWM_FILE string "XHCI firmware path and filename" - default "3rdparty/southbridge/amd/hudson/xhci.bin" + default "3rdparty/southbridge/amd/hudson/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON + default "3rdparty/southbridge/amd/yangtze/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE depends on HUDSON_XHCI_FWM
config HUDSON_IMC_FWM_FILE string "IMC firmware path and filename" - default "3rdparty/southbridge/amd/hudson/imc.bin" + default "3rdparty/southbridge/amd/hudson/imc.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON + default "3rdparty/southbridge/amd/yangtze/imc.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE depends on HUDSON_IMC_FWM
config HUDSON_GEC_FWM_FILE string "GEC firmware path and filename" - default "3rdparty/southbridge/amd/hudson/gec.bin" + default "3rdparty/southbridge/amd/hudson/gec.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON + default "3rdparty/southbridge/amd/yangtze/gec.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE depends on HUDSON_GEC_FWM
config HUDSON_FWM @@ -232,4 +241,10 @@ config HUDSON_LEGACY_FREE Select y if there is no keyboard controller in the system. This sets variables in AGESA and ACPI.
-endif # SOUTHBRIDGE_AMD_AGESA_HUDSON +endif # SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE + +if SOUTHBRIDGE_AMD_AGESA_YANGTZE + config AMD_SB_SPI_TX_LEN + int + default 64 +endif diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index a0319ab..e8d534d 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -46,6 +46,9 @@ void hudson_lpc_port80(void) byte = pci_read_config8(dev, 0x4a); byte |= 1 << 5; /* enable port 80 */ pci_write_config8(dev, 0x4a, byte); + byte = pci_read_config8(dev, 0x48); + byte |= 3 << 0; /* enable port 80 */ + pci_write_config8(dev, 0x48, byte); }
int s3_save_nvram_early(u32 dword, int size, int nvram_pos) diff --git a/src/southbridge/amd/agesa/hudson/sata.c b/src/southbridge/amd/agesa/hudson/sata.c index cc8bf95..bc1cd92 100644 --- a/src/southbridge/amd/agesa/hudson/sata.c +++ b/src/southbridge/amd/agesa/hudson/sata.c @@ -49,3 +49,9 @@ static const struct pci_driver sata0_driver __pci_driver = { .vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_ATI_SB900_SATA, }; + +static const struct pci_driver sata0_driver_ahci __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_SATA_AHCI, +}; diff --git a/src/southbridge/amd/agesa/hudson/sd.c b/src/southbridge/amd/agesa/hudson/sd.c index 941bb97..e37a67c 100644 --- a/src/southbridge/amd/agesa/hudson/sd.c +++ b/src/southbridge/amd/agesa/hudson/sd.c @@ -14,9 +14,10 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#include <console/console.h> #include <device/device.h> #include <delay.h> #include <device/pci.h> @@ -29,24 +30,33 @@ static void sd_init(struct device *dev) { u32 stepping;
+ if (dev->enabled == 0) { + /* turn off the SDHC controller in the PM regs */ + outb(0xE8, PM_INDEX); + outb(0x00, PM_DATA); + return; + } + stepping = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xFC);
+ dev = dev_find_slot(0, PCI_DEVFN(0x14, 7)); + struct southbridge_amd_agesa_hudson_config *sd_chip = (struct southbridge_amd_agesa_hudson_config *)(dev->chip_info);
- if (sd_chip->sd_mode == 3) { /* SD 3.0 mode */ + if (sd_chip->sd_mode == 3) { /* SD 3.0 mode */ pci_write_config32(dev, 0xA4, 0x31FEC8B2); pci_write_config32(dev, 0xA8, 0x00002503); pci_write_config32(dev, 0xB0, 0x02180C19); pci_write_config32(dev, 0xD0, 0x0000078B); } - else { /* SD 2.0 mode */ - if ((stepping & 0x0000000F) == 0) { /* Stepping A0 */ + else { /* SD 2.0 mode */ + if ((stepping & 0x0000000F)==0) { /* Stepping A0 */ pci_write_config32(dev, 0xA4, 0x31DE32B2); pci_write_config32(dev, 0xB0, 0x01180C19); pci_write_config32(dev, 0xD0, 0x0000058B); } - else { /* Stepping >= A1 */ + else { /* Stepping >= A1 */ pci_write_config32(dev, 0xA4, 0x31FE3FB2); pci_write_config32(dev, 0xB0, 0x01180C19); pci_write_config32(dev, 0xD0, 0x0000078B); diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c index 3b727b9..d6ca215 100644 --- a/src/southbridge/amd/agesa/hudson/sm.c +++ b/src/southbridge/amd/agesa/hudson/sm.c @@ -82,6 +82,7 @@
static void sm_init(device_t dev) { + setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS); }
static int lsmbus_recv_byte(device_t dev) diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index 1a63ce2..cedd367 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -61,7 +61,9 @@ int spi_xfer(struct spi_slave *slave, const void *dout, /* First byte is cmd which can not being sent through FIFO. */ u8 cmd = *(u8 *)dout++; u8 readoffby1; +#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE u8 readwrite; +#endif u8 bytesout, bytesin; u8 count;
@@ -71,8 +73,15 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
readoffby1 = bytesout ? 0 : 1;
+#if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE + write8(spibar + 0x1E, 5); + write8(spibar + 0x1F, bytesout); /* SpiExtRegIndx [5] - TxByteCount */ + write8(spibar + 0x1E, 6); + write8(spibar + 0x1F, bytesin); /* SpiExtRegIndx [6] - RxByteCount */ +#else readwrite = (bytesin + readoffby1) << 4 | bytesout; write8(spibar + 1, readwrite); +#endif write8(spibar + 0, cmd);
reset_internal_fifo_pointer();