Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40968 )
Change subject: soc/intel/tigerlake: Disable Thunderbolt PCIe root ports bus master
......................................................................
Patch Set 16:
(1 comment)
Patch Set 15:
Patch Set 15:
Verified with disabling BME (with Kconfig) at early stage (Patchset 15) disables PCIe resource allocation, which will then affect USB behind TBT dock enumeration at kernel.
The test results shows initial patchset would be preferable as disabling BME at late stage before handling to payload.
https://review.coreboot.org/c/coreboot/+/40968/16/src/soc/intel/tigerlake/ch...
File src/soc/intel/tigerlake/chip.c:
https://review.coreboot.org/c/coreboot/+/40968/16/src/soc/intel/tigerlake/ch...
PS16, Line 126:
: void platform_fsp_notify_status(enum fsp_notify_phase phase)
: {
: if (phase == END_OF_FIRMWARE) {
: struct device *dev;
:
: /* Disable Thunderbolt PCIe root ports bus master */
: dev = pcidev_path_on_root(SA_DEVFN_TBT0);
: if (dev)
: pci_dev_disable_bus_master(dev);
:
: dev = pcidev_path_on_root(SA_DEVFN_TBT1);
: if (dev)
: pci_dev_disable_bus_master(dev);
:
: dev = pcidev_path_on_root(SA_DEVFN_TBT2);
: if (dev)
: pci_dev_disable_bus_master(dev);
:
: dev = pcidev_path_on_root(SA_DEVFN_TBT3);
: if (dev)
: pci_dev_disable_bus_master(dev);
: }
: }
Since disabling the bus mastering this doesn't really depend on the FSP notify, maybe this shuld go in a BS_POST_DEVICE callback? That will happen post-FSP-S as well as post-PCI enumeration.
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