HAOUAS Elyes (ehaouas@noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6455
-gerrit
commit b8101ab7610c31c39467f407852d37f33070c66d Author: Elyes HAOUAS ehaouas@noos.fr Date: Fri Aug 1 15:39:31 2014 +0200
Add missing header guards
Change-Id: I065297cdb20dc0f31c1eddc03f0382d5c59ec7e7 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- src/mainboard/siemens/sitemp_g1p1/int15_func.h | 5 ++++- src/northbridge/amd/amdfam10/amdfam10.h | 2 +- src/northbridge/amd/amdfam10/nums.h | 3 +-- src/northbridge/amd/amdk8/amdk8.h | 1 - src/northbridge/amd/amdmct/amddefs.h | 5 +++++ src/northbridge/amd/amdmct/mct/mct_d_gcc.h | 4 ++++ src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h | 4 ++++ src/northbridge/intel/e7501/e7501.h | 5 +++++ src/northbridge/intel/e7505/e7505.h | 5 +++++ src/northbridge/intel/e7520/e7520.h | 5 +++++ src/northbridge/intel/e7525/e7525.h | 5 +++++ src/northbridge/intel/i82830/i82830.h | 5 +++++ src/northbridge/intel/i855/i855.h | 5 +++++ src/northbridge/via/cn400/cn400.h | 5 +++++ src/northbridge/via/cn700/cn700.h | 5 +++++ src/northbridge/via/cx700/registers.h | 5 +++++ src/southbridge/amd/amd8111/amd8111_smbus.h | 5 +++++ src/southbridge/intel/i82870/82870.h | 5 +++++ src/southbridge/nvidia/ck804/early_setup_ss.h | 5 +++++ src/southbridge/nvidia/ck804/early_smbus.h | 5 +++++ src/southbridge/nvidia/mcp55/early_setup_ss.h | 5 +++++ src/southbridge/ricoh/rl5c476/rl5c476.h | 6 +++++- src/southbridge/sis/sis966/early_setup_ss.h | 5 +++++ src/southbridge/ti/pci7420/pci7420.h | 4 ++++ src/southbridge/via/common/via_early_smbus.h | 5 +++++ src/southbridge/via/vt82c686/vt82c686.h | 5 +++++ 26 files changed, 113 insertions(+), 6 deletions(-)
diff --git a/src/mainboard/siemens/sitemp_g1p1/int15_func.h b/src/mainboard/siemens/sitemp_g1p1/int15_func.h index 26f679e..32e4284 100644 --- a/src/mainboard/siemens/sitemp_g1p1/int15_func.h +++ b/src/mainboard/siemens/sitemp_g1p1/int15_func.h @@ -20,7 +20,8 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#ifndef INT15_FUNC_H +#define INT15_FUNC_H typedef struct { u8 func00_LCD_panel_id; // Callback Sub-Function 00h - Get LCD Panel ID u8 func02_set_expansion; @@ -33,3 +34,5 @@ typedef struct { }INT15_function_extensions;
extern void install_INT15_function_extensions(INT15_function_extensions *); + +#endif /* INT15_FUNC_H */ diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 6e71b4e..c01d182 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -18,8 +18,8 @@ */
#ifndef AMDFAM10_H - #define AMDFAM10_H + /* Definitions of various FAM10 registers */ /* Function 0 */ #define HT_TRANSACTION_CONTROL 0x68 diff --git a/src/northbridge/amd/amdfam10/nums.h b/src/northbridge/amd/amdfam10/nums.h index 12bac5d..c1ecf7f 100644 --- a/src/northbridge/amd/amdfam10/nums.h +++ b/src/northbridge/amd/amdfam10/nums.h @@ -18,7 +18,6 @@ */
#ifndef AMDFAM10_NUMS_H - #define AMDFAM10_NUMS_H
#if CONFIG_MAX_PHYSICAL_CPUS > 8 @@ -37,4 +36,4 @@ //it could be more bigger #define HC_POSSIBLE_NUM 32
-#endif +#endif /* AMDFAM10_NUMS_H */ diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h index 05117f7..591244d 100644 --- a/src/northbridge/amd/amdk8/amdk8.h +++ b/src/northbridge/amd/amdk8/amdk8.h @@ -1,5 +1,4 @@ #ifndef AMDK8_H - #define AMDK8_H
#if CONFIG_K8_REV_F_SUPPORT diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h index 9efc1db..6ac9e64 100644 --- a/src/northbridge/amd/amdmct/amddefs.h +++ b/src/northbridge/amd/amdmct/amddefs.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef AMDDEFS_H +#define AMDDEFS_H + /* FIXME: this file should be moved to include/cpu/amd/amddefs.h */
/* Public Revisions - USE THESE VERSIONS TO MAKE COMPARE WITH CPULOGICALID RETURN VALUE*/ @@ -148,3 +151,5 @@ #define AMD_PKGTYPE_G34 3 #define AMD_PKGTYPE_ASB2 4 #define AMD_PKGTYPE_C32 5 + +#endif /* AMDDEFS_H */ diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h index e989ae3..72b141f 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h +++ b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef MCT_D_GCC_H +#define MCT_D_GCC_H
static inline void _WRMSR(u32 addr, u32 lo, u32 hi) { @@ -376,3 +378,5 @@ static u8 oemNodePresent_D(u8 Node, u8 *ret) *ret = 0; return 0; } + +#endif /* MCT_D_GCC_H */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h index abe6e7b..8024075 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef MCT_D_GCC_H +#define MCT_D_GCC_H static inline void _WRMSR(u32 addr, u32 lo, u32 hi) { __asm__ volatile ( @@ -358,3 +360,5 @@ static u8 oemNodePresent_D(u8 Node, u8 *ret) *ret = 0; return 0; } + +#endif /* MCT_D_GCC_H */ diff --git a/src/northbridge/intel/e7501/e7501.h b/src/northbridge/intel/e7501/e7501.h index 1e431b1..20d9f80 100644 --- a/src/northbridge/intel/e7501/e7501.h +++ b/src/northbridge/intel/e7501/e7501.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef E7501_H +#define E7501_H + /* * e7501.h: PCI configuration space for the Intel E7501 memory controller */ @@ -77,3 +80,5 @@ #define NERR_GLOBAL 0x44 /* Next global error register, 32 bits */ #define DRAM_FERR 0x80 /* DRAM first error register, 8 bits */ #define DRAM_NERR 0x82 /* DRAM next error register, 8 bits */ + +#endif /* E7501_H */ diff --git a/src/northbridge/intel/e7505/e7505.h b/src/northbridge/intel/e7505/e7505.h index 08b681a..d3a8089 100644 --- a/src/northbridge/intel/e7505/e7505.h +++ b/src/northbridge/intel/e7505/e7505.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef E7505_H +#define E7505_H + /* * e7505.h: PCI configuration space for the Intel E7501 memory controller */ @@ -82,3 +85,5 @@ #define NERR_GLOBAL 0x44 /* Next global error register, 32 bits */ #define DRAM_FERR 0x80 /* DRAM first error register, 8 bits */ #define DRAM_NERR 0x82 /* DRAM next error register, 8 bits */ + +#endif /* E7505_H */ diff --git a/src/northbridge/intel/e7520/e7520.h b/src/northbridge/intel/e7520/e7520.h index 61401e4..eb35a2c 100644 --- a/src/northbridge/intel/e7520/e7520.h +++ b/src/northbridge/intel/e7520/e7520.h @@ -1,3 +1,6 @@ +#ifndef E7520_H +#define E7520_H + #define IURBASE 0X14 #define MCHCFG0 0X50 #define MCHSCRB 0X52 @@ -37,3 +40,5 @@ #define DEVPRES1_D0F1 (1 << 5) #define DEVPRES1_D8F0 (1 << 1) #define MSCFG 0XF6 + +#endif /* E7520_H */ diff --git a/src/northbridge/intel/e7525/e7525.h b/src/northbridge/intel/e7525/e7525.h index 61401e4..6402c29 100644 --- a/src/northbridge/intel/e7525/e7525.h +++ b/src/northbridge/intel/e7525/e7525.h @@ -1,3 +1,6 @@ +#ifndef E7525_H +#define E7525_H + #define IURBASE 0X14 #define MCHCFG0 0X50 #define MCHSCRB 0X52 @@ -37,3 +40,5 @@ #define DEVPRES1_D0F1 (1 << 5) #define DEVPRES1_D8F0 (1 << 1) #define MSCFG 0XF6 + +#endif /* E7525_H */ diff --git a/src/northbridge/intel/i82830/i82830.h b/src/northbridge/intel/i82830/i82830.h index bdf7e51..7474beb 100644 --- a/src/northbridge/intel/i82830/i82830.h +++ b/src/northbridge/intel/i82830/i82830.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef I82830_H +#define I82830_H + #define RRBAR 0x48 /* Register Range Base Address (0x00000000) */ #define GCC0 0x50 /* GMCH Control #0 (0xa072) */ #define GCC1 0x52 /* GMCH Control #1 (0x0000) */ @@ -49,3 +52,5 @@ #define APBASE 0x10 /* Aperture Base Configuration (0x00000008) */ #define APSIZE 0xb4 /* Apterture Size (0x00) */ #define ATTBASE 0xb8 /* Aperture Translation Table Base (0x00000000) */ + +#endif /* I82830_H */ diff --git a/src/northbridge/intel/i855/i855.h b/src/northbridge/intel/i855/i855.h index 8786fd7..1d438eb 100644 --- a/src/northbridge/intel/i855/i855.h +++ b/src/northbridge/intel/i855/i855.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef I855_H +#define I855_H + /* Host-Hub Interface Bridge */ #define GMC 0x50 /* GMCH Misc. Control (0x0000) */ #define GGC 0x52 /* GMCH Graphics Control (0x0030) */ @@ -74,3 +77,5 @@ #define DRT_TRAS_MIN_7 (1 << 9) #define DRT_TRAS_MIN_6 (2 << 9) #define DRT_TRAS_MIN_5 (3 << 9) + +#endif /* I855_H */ diff --git a/src/northbridge/via/cn400/cn400.h b/src/northbridge/via/cn400/cn400.h index 2df30a6..e593b6f 100644 --- a/src/northbridge/via/cn400/cn400.h +++ b/src/northbridge/via/cn400/cn400.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef CN400_H +#define CN400_H + #ifndef __PRE_RAM__ // HACK static inline void cn400_noop(device_t dev) @@ -54,3 +57,5 @@ static inline void cn400_noop(device_t dev) #define RAM_COMMAND_MSR_LOW (const char) 0x03 #define RAM_COMMAND_CBR (const char) 0x04 #define RAM_COMMAND_MSR_HIGH (const char) 0x05 + +#endif /* CN400_H */ diff --git a/src/northbridge/via/cn700/cn700.h b/src/northbridge/via/cn700/cn700.h index ff1d4b3..178a0e4 100644 --- a/src/northbridge/via/cn700/cn700.h +++ b/src/northbridge/via/cn700/cn700.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef CN700_H +#define CN700_H + #if !defined (__PRE_RAM__) // HACK static inline void cn700_noop(device_t dev) @@ -54,3 +57,5 @@ static inline void cn700_noop(device_t dev) #define RAM_COMMAND_PRECHARGE 0x2 #define RAM_COMMAND_MRS 0x3 #define RAM_COMMAND_CBR 0x4 + +#endif /* CN700_H */ diff --git a/src/northbridge/via/cx700/registers.h b/src/northbridge/via/cx700/registers.h index 67c3da4..10b486b 100644 --- a/src/northbridge/via/cx700/registers.h +++ b/src/northbridge/via/cx700/registers.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef REGISTERS_H +#define REGISTERS_H + /* CX700 has 48 bytes of scratch registers in D0F4 starting at Reg. 0xd0 */ #define SCRATCH_REG_BASE 0xd0 #define SCRATCH_RANK_0 0xd0 @@ -42,3 +45,5 @@ #define DDRII_333 0x2 #define DDRII_266 0x1 #define DDRII_200 0x0 + +#endif /* REGISTERS_H */ diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.h b/src/southbridge/amd/amd8111/amd8111_smbus.h index 00f8f50..03cf1ea 100644 --- a/src/southbridge/amd/amd8111/amd8111_smbus.h +++ b/src/southbridge/amd/amd8111/amd8111_smbus.h @@ -1,3 +1,6 @@ +#ifndef AMD8111_SMBUS_H +#define AMD8111_SMBUS_H + #include <device/smbus_def.h>
#define SMBGSTATUS 0xe0 @@ -323,3 +326,5 @@ static int do_smbus_block_write(unsigned smbus_io_base, unsigned device, unsigne } return 0; } + +#endif /* AMD8111_SMBUS_H */ diff --git a/src/southbridge/intel/i82870/82870.h b/src/southbridge/intel/i82870/82870.h index b576cc1..4c17c65 100644 --- a/src/southbridge/intel/i82870/82870.h +++ b/src/southbridge/intel/i82870/82870.h @@ -1,3 +1,6 @@ +#ifndef I82870_82870_H +#define I82870_82870_H + /* for io apic 1461 */ #define MBAR 0x10 #define ABAR 0x40 @@ -12,3 +15,5 @@ #define STRP_HPCAP 0x0002 // Hot-plug capable (Hx_SLOT zero/nonzero)
#define ACNF_SYNCPH 0x0010 // PCI(-X) input clock is synchronous to hub input clock + +#endif /* I82870_82870_H */ diff --git a/src/southbridge/nvidia/ck804/early_setup_ss.h b/src/southbridge/nvidia/ck804/early_setup_ss.h index 9f89595..4945c1b 100644 --- a/src/southbridge/nvidia/ck804/early_setup_ss.h +++ b/src/southbridge/nvidia/ck804/early_setup_ss.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef EARLY_SETUP_SS_H +#define EARLY_SETUP_SS_H + static const unsigned int pcie_ss_tbl[] = { 0x0C504103f, 0x0C504103f, @@ -218,3 +221,5 @@ static const unsigned int cpu_ss_tbl[] = { 0x0C5039037, 0x0C5039037, }; + +#endif /* EARLY_SETUP_SS_H */ diff --git a/src/southbridge/nvidia/ck804/early_smbus.h b/src/southbridge/nvidia/ck804/early_smbus.h index cf25403..c8a52ed 100644 --- a/src/southbridge/nvidia/ck804/early_smbus.h +++ b/src/southbridge/nvidia/ck804/early_smbus.h @@ -1,5 +1,10 @@ +#ifndef EARLY_SMBUS_H +#define EARLY_SMBUS_H + int ck804_smbus_read_byte(unsigned int, unsigned int, unsigned); int ck804_smbus_write_byte(unsigned int, unsigned int, unsigned int, unsigned char); void enable_smbus(void); int smbus_read_byte(unsigned int, unsigned int); int smbus_write_byte(unsigned int, unsigned int, unsigned char); + +#endif /* EARLY_SMBUS_H */ diff --git a/src/southbridge/nvidia/mcp55/early_setup_ss.h b/src/southbridge/nvidia/mcp55/early_setup_ss.h index 0aadc73..8eb8b34 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_ss.h +++ b/src/southbridge/nvidia/mcp55/early_setup_ss.h @@ -19,6 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef EARLY_SETUP_SS_H +#define EARLY_SETUP_SS_H + static const unsigned int pcie_ss_tbl[] = { 0x0C504103f, 0x0C504103f, @@ -219,3 +222,5 @@ static const unsigned int cpu_ss_tbl[] = { 0x0C5039037, 0x0C5039037, }; + +#endif /* EARLY_SETUP_SS_H */ diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.h b/src/southbridge/ricoh/rl5c476/rl5c476.h index 71966a1..5818ed3 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.h +++ b/src/southbridge/ricoh/rl5c476/rl5c476.h @@ -21,8 +21,10 @@ /* rl5c476 routines and defines*/
-#include <stdint.h> +#ifndef RL5C476_H +#define RL5C476_H
+#include <stdint.h>
/* the 16 bit control structure for ricoh cardbus bridge */ typedef struct pc16reg { @@ -92,3 +94,5 @@ typedef struct pc16reg { u8 resv9; u8 smpga0; } __attribute__ ((packed)) pc16reg_t; + +#endif /* RL5C476_H */ diff --git a/src/southbridge/sis/sis966/early_setup_ss.h b/src/southbridge/sis/sis966/early_setup_ss.h index b6aa7d7..44c067d 100644 --- a/src/southbridge/sis/sis966/early_setup_ss.h +++ b/src/southbridge/sis/sis966/early_setup_ss.h @@ -19,6 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef EARLY_SETUP_SS_H +#define EARLY_SETUP_SS_H + static const unsigned int pcie_ss_tbl[] = { 0x0C504103f, 0x0C504103f, @@ -218,3 +221,5 @@ static const unsigned int cpu_ss_tbl[] = { 0x0C5039037, 0x0C5039037, }; + +#endif /* EARLY_SETUP_SS_H */ diff --git a/src/southbridge/ti/pci7420/pci7420.h b/src/southbridge/ti/pci7420/pci7420.h index f71fe17..6c92ada 100644 --- a/src/southbridge/ti/pci7420/pci7420.h +++ b/src/southbridge/ti/pci7420/pci7420.h @@ -18,6 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef PCI7420_H +#define PCI7420_H // 0844d060 (old) #define SYSCTL 0x80 // 08405061 #define RIMUX (1 << 0) @@ -47,3 +49,5 @@ #define INTB 1 #define INTC 2 #define INTD 3 + +#endif /* PCI7420_H */ diff --git a/src/southbridge/via/common/via_early_smbus.h b/src/southbridge/via/common/via_early_smbus.h index aca920b..07c2d52 100644 --- a/src/southbridge/via/common/via_early_smbus.h +++ b/src/southbridge/via/common/via_early_smbus.h @@ -35,6 +35,9 @@ * @endcode */
+#ifndef VIA_EARLY_SMBUS_H +#define VIA_EARLY_SMBUS_H + /** * \brief SMBus IO ports in relation to the base IO port */ @@ -54,3 +57,5 @@
#include <device/early_smbus.h> #include <arch/io.h> + +#endif /* VIA_EARLY_SMBUS_H */ diff --git a/src/southbridge/via/vt82c686/vt82c686.h b/src/southbridge/via/vt82c686/vt82c686.h index 7d2ac52..85cf7b9 100644 --- a/src/southbridge/via/vt82c686/vt82c686.h +++ b/src/southbridge/via/vt82c686/vt82c686.h @@ -25,6 +25,9 @@ * Link: http://www.datasheet4u.com/html/V/T/8/VT82C686B_VIA.pdf.html */
+#ifndef VT82C686_H +#define VT82C686_H + /* Super I/0 Configuration Registers. */ /* Any registers not listed here are reserved. */ #define VT82C686_SIO_DEV_ID 0xe0 /* Super-I/O Device ID */ @@ -53,3 +56,5 @@ PCI_DEVICE_ID_VIA_82C686_4 0x3057 // Function 4, Power Management PCI_DEVICE_ID_VIA_82C686_5 0x3058 // Function 5, AC'97 Codec PCI_DEVICE_ID_VIA_82C686_6 0x3068 // Function 6, MC'97 Codec */ + +#endif /* VT82C686_H */