Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50510 )
Change subject: soc/amd/cezanne: Fill FADT and MADT ......................................................................
soc/amd/cezanne: Fill FADT and MADT
The MADT doesn't populate the IO-APICs yet since we need FSP to configure those.
The FADT differs from picasso because the duty_offset is supposed to be 0. I also changed the extended to use the MMIO addresses
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: Ib6c3a01084a0de33894885b47c637a292d252ed4 --- M src/soc/amd/cezanne/acpi.c M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/include/soc/acpi.h M src/soc/amd/cezanne/include/soc/iomap.h 4 files changed, 115 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/50510/1
diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index c7752bf..c9f4a5f 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -3,6 +3,13 @@ /* ACPI - create the Fixed ACPI Description Tables (FADT) */
#include <acpi/acpi.h> +#include <amdblocks/acpimmio.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <soc/acpi.h> +#include <soc/iomap.h> +#include <types.h> +#include "chip.h"
unsigned long acpi_fill_mcfg(unsigned long current) { @@ -18,7 +25,22 @@
unsigned long acpi_fill_madt(unsigned long current) { - /* TODO */ + unsigned int i; + uint8_t irq; + uint8_t flags; + + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + current += acpi_create_madt_irqoverride( + (acpi_madt_irqoverride_t *)current, + MP_BUS_ISA, 0, 2, + MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT); + current += acpi_create_madt_irqoverride( + (acpi_madt_irqoverride_t *)current, + MP_BUS_ISA, ACPI_SCI_IRQ, ACPI_SCI_IRQ, + MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); + return current; }
@@ -28,5 +50,80 @@ */ void acpi_fill_fadt(acpi_fadt_t *fadt) { - /* TODO */ + const struct soc_amd_cezanne_config *cfg = config_of_soc(); + + printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); + + fadt->sci_int = ACPI_SCI_IRQ; + + if (permanent_smi_handler()) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + } + + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; + fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; + fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; + fadt->gpe0_blk = ACPI_GPE0_BLK; + + fadt->pm1_evt_len = 4; /* 32 bits */ + fadt->pm1_cnt_len = 2; /* 16 bits */ + fadt->pm_tmr_len = 4; /* 32 bits */ + fadt->gpe0_blk_len = 8; /* 64 bits */ + + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + fadt->duty_offset = 0; /* Not supported */ + fadt->duty_width = 0; /* Not supported */ + fadt->day_alrm = RTC_DATE_ALARM; + fadt->mon_alrm = 0; + fadt->century = RTC_ALT_CENTURY; + fadt->iapc_boot_arch = cfg->fadt_boot_arch; /* legacy free default */ + fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ + fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_32BIT_TIMER | + ACPI_FADT_PCI_EXPRESS_WAKE | + ACPI_FADT_PLATFORM_CLOCK | + ACPI_FADT_S4_RTC_VALID | + ACPI_FADT_REMOTE_POWER_ON; + fadt->flags |= cfg->fadt_flags; /* additional board-specific flags */ + + fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ + fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ + + fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ + fadt->x_firmware_ctl_h = 0; + + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_MEMORY; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = (u32)acpimmio_pmio + ACPI_MMIO_PM_EVT_BLK; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_MEMORY; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = (u32)acpimmio_pmio + ACPI_MMIO_PM1_CNT_BLK; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_MEMORY; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = (u32)acpimmio_pmio + ACPI_MMIO_PM_TMR_BLK; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_MEMORY; + fadt->x_gpe0_blk.bit_width = 64; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = (u32)acpimmio_pmio + ACPI_MMIO_GPE0_BLK; + fadt->x_gpe0_blk.addrh = 0x0; } diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index b4e94a4..76fd444 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -7,6 +7,10 @@
struct soc_amd_cezanne_config { struct soc_amd_common_config common_config; + + /* Options for these are in src/arch/x86/include/acpi/acpi.h */ + uint16_t fadt_boot_arch; + uint32_t fadt_flags; };
#endif /* CEZANNE_CHIP_H */ diff --git a/src/soc/amd/cezanne/include/soc/acpi.h b/src/soc/amd/cezanne/include/soc/acpi.h index 6927d93..dbcf867 100644 --- a/src/soc/amd/cezanne/include/soc/acpi.h +++ b/src/soc/amd/cezanne/include/soc/acpi.h @@ -3,5 +3,11 @@ #ifndef AMD_CEZANNE_ACPI_H #define AMD_CEZANNE_ACPI_H
+#define ACPI_SCI_IRQ 9 + +/* RTC Registers */ +#define RTC_DATE_ALARM 0x0D +#define RTC_ALT_CENTURY 0x32 +#define RTC_CENTURY 0x48
#endif /* AMD_CEZANNE_ACPI_H */ diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index 73640f5..509b0f7 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -29,4 +29,10 @@ #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) #define SMB_BASE_ADDR 0x0b00
+#define ACPI_MMIO_BASE 0x500 +#define ACPI_MMIO_PM_EVT_BLK (ACPI_MMIO_BASE + 0x00) +#define ACPI_MMIO_PM1_CNT_BLK (ACPI_MMIO_BASE + 0x04) +#define ACPI_MMIO_PM_TMR_BLK (ACPI_MMIO_BASE + 0x08) +#define ACPI_MMIO_GPE0_BLK (ACPI_MMIO_BASE + 0x14) + #endif /* AMD_CEZANNE_IOMAP_H */