[coreboot-gerrit] Change in coreboot[master]: nb/intel/i440bx: Refactor ACPI code

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41049 )

Change subject: nb/intel/i440bx: Refactor ACPI code
......................................................................

nb/intel/i440bx: Refactor ACPI code

Bring DRB7 OpRegion and top-of-memory indicator inside NB device.

Use more concise ASL 2.0 syntax for TOM calculations.

Change-Id: I2c74ef30a9bb48e02154f963b1ca3a4f5f3004df
Signed-off-by: Keith Hui 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41049
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
Reviewed-by: Patrick Georgi 
---
M src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl
1 file changed, 13 insertions(+), 16 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Georgi: Looks good to me, approved
  Angel Pons: Looks good to me, but someone else must approve

diff --git a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl
index fe66f39..ce71aed 100644
--- a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl
+++ b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl
@@ -1,21 +1,19 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

-/* i440bx Northbridge */
+/* i440bx Northbridge resources that sits on _SB.PCI0 */
 Device (NB)
 {
    Name(_ADR, 0x00000000)
    OperationRegion(PCIC, PCI_Config, 0x00, 0x100)
-}
-
-Field (NB.PCIC, AnyAcc, NoLock, Preserve)
-{
-	Offset (0x67),	// DRB7
-	DRB7,	8,
-}
-
-Method(TOM1, 0) {
-	/* Multiply by 8MB to get TOM */
-	Return(ShiftLeft(DRB7, 23))
+	Field (PCIC, ByteAcc, NoLock, Preserve)
+	{
+		Offset (0x67),	// DRB7
+		DRB7,	8,
+	}
+	Method(TOM1, 0) {
+		/* Multiply by 8MB to get TOM */
+		Return(DRB7 << 23)
+	}
 }

Method(_CRS, 0) {
@@ -60,10 +58,9 @@
     * 32bit (0x00000000 - TOM1) will wrap and give the same
     * result as 64bit (0x100000000 - TOM1).
     */
-	Store(TOM1, MM1B)
-	ShiftLeft(0x10000000, 4, Local0)
-	Subtract(Local0, TOM1, Local0)
-	Store(Local0, MM1L)
+	MM1B = _SB.PCI0.NB.TOM1
+	Local0 = 0x10000000 << 4
+	MM1L = Local0 - MM1B

Return(TMP)
 }