Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60139 )
Change subject: mb/google/guybrush: Enable PSP_S0I3_RESUME_VERSTAGE ......................................................................
mb/google/guybrush: Enable PSP_S0I3_RESUME_VERSTAGE
Enable PSP_S0I3_RESUME_VERSTAGE for all guybrush based boards. This will cause verstage to run during s0i3 resume. The TPM will be reinitialized in verstage during s0i3 resume. This is necessary on guybrush boards because the TPM_RST_L pin is asserted by the SOC in S0i3.
BUG=b:200578885 BRANCH=None TEST=TPM initialized after s0i3
Change-Id: I9d64fe92ffc67a421be6d5e013e636332ce86dd5 Signed-off-by: Rob Barnes robbarnes@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/60139 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Paul Menzel paulepanter@mailbox.org Reviewed-by: Raul Rangel rrangel@chromium.org Reviewed-by: Karthik Ramasubramanian kramasub@google.com --- M src/mainboard/google/guybrush/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Raul Rangel: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved
diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index 7d9cd3d..ded66ab 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -39,6 +39,7 @@ select PCIEXP_COMMON_CLOCK select PCIEXP_L1_SUB_STATE select PSP_DISABLE_POSTCODES + select PSP_S0I3_RESUME_VERSTAGE if VBOOT_STARTS_BEFORE_BOOTBLOCK select SOC_AMD_CEZANNE select SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF select SOC_AMD_COMMON_BLOCK_USE_ESPI
3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one.