Hello Jason Glenesk,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/45056
to review the following change.
Change subject: soc/amd/picasso/acpi: Fix hang caused by IVRS ......................................................................
soc/amd/picasso/acpi: Fix hang caused by IVRS
MADT does not contain an entry for the second ioapic described in the IVRS.
Add second ioapic to MADT.
Cq-Depend: chrome-internal:3247427, chrome-internal:3247427 BUG=b:166519072 TEST=Boot fully to morphius board with and without amd_iommu kernel parameter. Dump MADT and IVRS tables. Cross check ioapic entries in MADT against IVRS. Confirm IVRS contains no alignment gaps/corruption.
Signed-off-by: Jason Glenesk jason.glenesk@amd.corp-partner.google.com Change-Id: Ic4a2e9b71dba948e8a4907e5f97131426d8a4a3e --- M src/soc/amd/picasso/acpi.c M src/soc/amd/picasso/include/soc/smu.h 2 files changed, 20 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/45056/1
diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 1b9c0ca..dc4a167 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -26,6 +26,7 @@ #include <soc/gpio.h> #include <version.h> #include "chip.h" +#include <soc/smu.h>
unsigned long acpi_fill_mcfg(unsigned long current) { @@ -45,13 +46,29 @@ unsigned int i; uint8_t irq; uint8_t flags; + uint32_t nb_ioapic_base; + uint8_t ioapic_id;
/* create all subtables for processors */ current = acpi_create_madt_lapics(current);
- /* Write Kern IOAPIC, only one */ + /* Lapics use IDs 0 - max logical cpus - 1. FCH ioapic ID uses the next ID*/ + ioapic_id = CONFIG_MAX_CPUS; + + /* Write FCH IOAPIC */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, - CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); + ioapic_id, IO_APIC_ADDR, 0); + + /* Read base address assigned to gnb ioapic */ + pci_write_config32(SOC_GNB_DEV, SMU_INDEX_ADDR, REG_NB_IOAPIC_BASE); + nb_ioapic_base = pci_read_config32(SOC_GNB_DEV, SMU_DATA_ADDR); + + /* GNB uses the next ID*/ + ioapic_id++; + + /* Write GNB IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, + ioapic_id, nb_ioapic_base, IO_APIC_INTERRUPTS);
/* 0: mean bus 0--->ISA */ /* 0: PIC 0 */ diff --git a/src/soc/amd/picasso/include/soc/smu.h b/src/soc/amd/picasso/include/soc/smu.h index 128f4c4..bc9f4f3 100644 --- a/src/soc/amd/picasso/include/soc/smu.h +++ b/src/soc/amd/picasso/include/soc/smu.h @@ -12,6 +12,7 @@ #define REG_ADDR_MESG_ID 0x3b10528 #define REG_ADDR_MESG_RESP 0x3b10564 #define REG_ADDR_MESG_ARGS_BASE 0x0b10998 +#define REG_NB_IOAPIC_BASE 0x13b102f0
/* Argument 0-5 indexed locations are contiguous */ #define SMU_NUM_ARGS 6