Ricardo Ribalda Delgado (ricardo.ribalda@gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17980
-gerrit
commit bbef554d77b0eecb0b785e78a4f5a93bbcf6b31e Author: Ricardo Ribalda Delgado ricardo.ribalda@gmail.com Date: Wed Dec 28 15:16:22 2016 +0100
amd/pi: Make BottomIo position configurable
Some PCI peripherals, such as FPGA accelerators, require a great amount of memory mapped IO. This patch allows the user to select at build time the bottom IO to leave enough space for such devices.
We cannot calculate this value at runtime because it has to be set before the PCI devices are enumerated.
Change-Id: Ic590e8aa8b91ff89877cbff6afd10614d33dcf8d Credit-to: Kyösti Mälkki kyosti.malkki@gmail.com Signed-off-by: Ricardo Ribalda Delgado ricardo.ribalda@gmail.com --- src/northbridge/amd/pi/Kconfig | 12 ++++++++++++ src/northbridge/amd/pi/agesawrapper.c | 3 ++- 2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index 122b0e6..f5f36f8 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -20,6 +20,18 @@ config NORTHBRIDGE_AMD_PI
if NORTHBRIDGE_AMD_PI
+config BOTTOMIO_POSITION + hex "Bottom of 32-bit IO space" + default 0xD0000000 + help + If PCI peripherals with big BARs are connected to the system + the bottom of the IO must be decreased to allocate such + devices. + + Declare the beginning of the 128MB-aligned MMIO region. This + option is useful when PCI peripherals requesting large address + ranges are present. + config CONSOLE_VGA_MULTI bool default n diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index 8e16e75..0fe8eab 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -140,7 +140,8 @@ AGESA_STATUS agesawrapper_amdinitpost(void) // the compiler to flag the error if CONFIG_GFXUMA is not set. PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE; PostParams->MemConfig.UmaSize = 0; - PostParams->MemConfig.BottomIo = (UINT16)(0xD0000000 >> 24); + PostParams->MemConfig.BottomIo = (UINT16) + (CONFIG_BOTTOMIO_POSITION >> 24); status = AmdInitPost (PostParams); printk( BIOS_SPEW,