Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32784 )
Change subject: src/northbridge: Remove unneeded include <arch/io.h> ......................................................................
src/northbridge: Remove unneeded include <arch/io.h>
Change-Id: I52ace93ae6f802723823955ac349ed54dc064aaa Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/32784 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/northbridge/intel/gm45/early_reset.c M src/northbridge/intel/gm45/romstage.c M src/northbridge/intel/haswell/raminit.c M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/romstage.c M src/northbridge/intel/x4x/raminit.c 10 files changed, 0 insertions(+), 10 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved
diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c index 3f095a2..b5aa804 100644 --- a/src/northbridge/intel/gm45/early_reset.c +++ b/src/northbridge/intel/gm45/early_reset.c @@ -15,7 +15,6 @@ */
#include <types.h> -#include <arch/io.h> #include <cf9_reset.h> #include <device/pci_ops.h>
diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index 15d3c3a..38f2d5f 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -18,7 +18,6 @@ #include <cbmem.h> #include <romstage_handoff.h> #include <console/console.h> -#include <arch/io.h> #include <device/pci_ops.h> #include <arch/acpi.h> #include <cpu/x86/lapic.h> diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 96dc94e..050dbd1 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -15,7 +15,6 @@
#include <console/console.h> #include <string.h> -#include <arch/io.h> #include <cbmem.h> #include <arch/cbfs.h> #include <cbfs.h> diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 74407c1..797ea12 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -18,7 +18,6 @@ #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <arch/io.h> #include <cf9_reset.h> #include <device/mmio.h> #include <device/device.h> diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 144905f..282765e 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */
-#include <arch/io.h> #include <cf9_reset.h> #include <device/mmio.h> #include <device/pci_ops.h> diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index a3e6c39..41fb0f6 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -17,7 +17,6 @@ * so this one is named with prefix mainboard. */
-#include <arch/io.h> #include <timestamp.h> #include <console/console.h> #include <device/pci_ops.h> diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index e60c378..2ebeaf0 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -21,7 +21,6 @@ #include <cf9_reset.h> #include <string.h> #include <arch/cpu.h> -#include <arch/io.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <cbmem.h> diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index a35d9d8..f032b8a 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -18,7 +18,6 @@ #include <bootmode.h> #include <cf9_reset.h> #include <string.h> -#include <arch/io.h> #include <device/pci_ops.h> #include <arch/cpu.h> #include <cbmem.h> diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 064d042..76b3088 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -17,7 +17,6 @@
#include <stdint.h> #include <console/console.h> -#include <arch/io.h> #include <cf9_reset.h> #include <device/pci_ops.h> #include <cpu/x86/lapic.h> diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 60d3b55..7fed1ef 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */
-#include <arch/io.h> #include <device/pci_ops.h> #include <cbmem.h> #include <cf9_reset.h>