[coreboot-gerrit] Change in coreboot[master]: mb/google/hatch: Enable LPIT inclusion in DSDT

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34175 )

Change subject: mb/google/hatch: Enable LPIT inclusion in DSDT
......................................................................

mb/google/hatch: Enable LPIT inclusion in DSDT

Include the lpit.asl file in Hatch's DSDT definition.

BUG=b:130764684
BRANCH=none
TEST=compiles

Change-Id: If8ebff3db091257e8452869636c0e024f3123e8b
Signed-off-by: Tim Wawrzynczak 
---
M src/mainboard/google/hatch/dsdt.asl
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/34175/1

diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl
index 243c627..87e98ea 100644
--- a/src/mainboard/google/hatch/dsdt.asl
+++ b/src/mainboard/google/hatch/dsdt.asl
@@ -51,6 +51,9 @@
    /* Chipset specific sleep states */
    #include <soc/intel/cannonlake/acpi/sleepstates.asl>

+        /* Low power idle table */
+        #include <soc/intel/cannonlake/acpi/lpit.asl>
+
    /* Chrome OS Embedded Controller */
    Scope (_SB.PCI0.LPCB)
    {