Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34773 )
Change subject: soc/mediatek: dsi: Support sending MIPI init commands ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34773/12/src/soc/mediatek/common/ds... File src/soc/mediatek/common/dsi.c:
https://review.coreboot.org/c/coreboot/+/34773/12/src/soc/mediatek/common/ds... PS12, Line 318: clrsetbits_le32(cmdq0 + ((cmdq_off + i) & (0xfffffffc)),
This is pretty nasty. You're reading and writing each peripheral register four times. […]
Actually, I've seen this same pattern over and over again, almost every SPI/I2C/whatever driver has the same problem with their FIFO registers. I think this would be a good opportunity to add a helper macro that deals with the tricky bits of this operation. I've tried to write that with CB:34817. With that, I think you could reduce this to:
u32 prefix = (type << 8) | config; int prefsz = 2; if (len > 2) { prefsz = 4; prefix |= len << 16; } buffer_to_fifo32_prefix(tx_buf, prefix, prefsz, len + prefsz, &dsi0->dsi_cmdq, 4, 4); write32(&dsi0->dsi_cmdq_size, DIV_ROUND_UP(len + prefsz, 4));
Let me know what you think!