[coreboot-gerrit] Change in ...coreboot[master]: sb/intel/spi: Check for the SPI lock bit during runtime

[Arthur Heymans (Code Review)]

Arthur Heymans has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33388 )

Change subject: sb/intel/spi: Check for the SPI lock bit during runtime
......................................................................

sb/intel/spi: Check for the SPI lock bit during runtime

The SPI swseq controller can be locked in other parts of the code, for
instance when it's locked down in the finalize section. The driver
has to be made aware of that. The simpler solution is to not keep
track of the state and simply read out the lock bit on each SPI
transfer.

Change-Id: Ifcd5121b89d6f80fc1c1368786982d0d9fa1bf61
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33388
Tested-by: build bot (Jenkins) 
Reviewed-by: Nico Huber 
Reviewed-by: Angel Pons 
---
M src/southbridge/intel/common/spi.c
1 file changed, 12 insertions(+), 6 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved
  Angel Pons: Looks good to me, but someone else must approve

diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index f447515..d9a77c3 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -38,8 +38,6 @@

static int spi_is_multichip(void);

-static int g_ichspi_lock = 0;
-
 struct ich7_spi_regs {
    uint16_t spis;
    uint16_t spic;
@@ -294,7 +292,6 @@
    	cntlr->data = (uint8_t *)ich7_spi->spid;
    	cntlr->databytes = sizeof(ich7_spi->spid);
    	cntlr->status = (uint8_t *)&ich7_spi->spis;
-		g_ichspi_lock = readw_(&ich7_spi->spis) & HSFS_FLOCKDN;
    	cntlr->control = &ich7_spi->spic;
    	cntlr->bbar = &ich7_spi->bbar;
    	cntlr->preop = &ich7_spi->preop;
@@ -304,7 +301,6 @@
    	ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800);
    	cntlr->ich9_spi = ich9_spi;
    	hsfs = readw_(&ich9_spi->hsfs);
-		g_ichspi_lock = hsfs & HSFS_FLOCKDN;
    	cntlr->hsfs = hsfs;
    	cntlr->opmenu = ich9_spi->opmenu;
    	cntlr->menubytes = sizeof(ich9_spi->opmenu);
@@ -336,6 +332,16 @@
    pci_write_config8(dev, 0xdc, bios_cntl | 0x1);
 }

+static int spi_locked(void)
+{
+	struct ich_spi_controller *cntlr = &g_cntlr;
+	if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) {
+		return !!(readw_(&cntlr->ich7_spi->spis) & HSFS_FLOCKDN);
+	} else {
+		return !!(readw_(&cntlr->ich9_spi->hsfs) | HSFS_FLOCKDN);
+	}
+}
+
 static void spi_init_cb(void *unused)
 {
    spi_init();
@@ -407,7 +413,7 @@

trans->opcode = trans->out[0];
    spi_use_out(trans, 1);
-	if (!g_ichspi_lock) {
+	if (!spi_locked()) {
    	/* The lock is off, so just use index 0. */
    	writeb_(trans->opcode, cntlr->opmenu);
    	optypes = readw_(cntlr->optype);
@@ -552,7 +558,7 @@
    	 * in order to prevent the Management Engine from
    	 * issuing a transaction between WREN and DATA.
    	 */
-		if (!g_ichspi_lock)
+		if (!spi_locked())
    		writew_(trans.opcode, cntlr->preop);
    	return 0;
    }