[coreboot-gerrit] [M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes

[Keith Hui (Code Review)]

Attention is currently required from: Angel Pons, Bill XIE, Nicholas Chin.

Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email )

Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
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Patch Set 7:

(1 comment)

File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c:

https://review.coreboot.org/c/coreboot/+/85413/comment/6a7b8949_f1de0df4?usp... :
PS7, Line 104: 0x40
> The values of the bit fields of X_QSW_SEL2,3,4 (with X_QSW_SEL4 being the LSB, 1 meaning high, 0 mea […]

Thanks Bill. You made history. :)

So the values we need are: 0x70, 0x40, 0x20.

I am now reworking this patch, moving everything to ramstage and adding the code needed to do the actual IFD flashing, so I may not be able to update this patch further in its current form, but edit this patch with the values above and see how it works. If it still exhibits issues with PCIEX1_2, then it is something else, not because we set the GPIOs wrong.

Another fun thing to try is, if you have a PCIe card that can do x2 or x4, is to set the PCIEPCS1 strap to 0x1, making the _3 slot 2x, and see how this patch reacts with a card in _2. In this mode, _1 would not work.