[coreboot-gerrit] Change in coreboot[master]: soc/intel: Hook up `SOC_INTEL_DISABLE_IGD` to `InternalGfx` UPD

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52100 )

Change subject: soc/intel: Hook up `SOC_INTEL_DISABLE_IGD` to `InternalGfx` UPD
......................................................................

soc/intel: Hook up `SOC_INTEL_DISABLE_IGD` to `InternalGfx` UPD

Commit 0591348833f730a42e74039d8e2d957ec94a39d5 introduced this Kconfig
option inside soc/intel/common scope. However, it was only hooked up in
commit d74cd60b8159c3928dba318e6387f200ff3bb0e7 for Alder Lake, and in
commit 99157c1f4a80556462ca22a4ade87b2c8d09e674 for Tiger Lake. Hook up
the `SOC_INTEL_DISABLE_IGD` Kconfig option to the `InternalGfx` UPD.

Change-Id: Icd1379a835b445a6d4b028ebde5a3e355ee5b67b
Signed-off-by: Angel Pons 
---
M src/soc/intel/cannonlake/romstage/fsp_params.c
M src/soc/intel/icelake/romstage/fsp_params.c
M src/soc/intel/jasperlake/romstage/fsp_params.c
M src/soc/intel/skylake/romstage/fsp_params.c
4 files changed, 7 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/52100/1

diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index d55741f..c1fe5a7 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -12,6 +12,7 @@
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
 #include <soc/romstage.h>
+#include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>

#include "../chip.h"
@@ -29,7 +30,8 @@
     * Probe for no IGD and disable InternalGfx and panel power to prevent a
     * crash in FSP-M.
     */
-	if (dev && dev->enabled && pci_read_config16(SA_DEV_IGD, PCI_VENDOR_ID) != 0xffff) {
+	const bool igd_on = !CONFIG(SOC_INTEL_DISABLE_IGD) && dev && dev->enabled;
+	if (igd_on && pci_read_config16(SA_DEV_IGD, PCI_VENDOR_ID) != 0xffff) {
    	/* Set IGD stolen size to 64MB. */
    	m_cfg->InternalGfx = 1;
    	m_cfg->IgdDvmt50PreAlloc = 2;
diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c
index 0801da2..a5311d9 100644
--- a/src/soc/intel/icelake/romstage/fsp_params.c
+++ b/src/soc/intel/icelake/romstage/fsp_params.c
@@ -16,8 +16,8 @@
    const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
    uint32_t mask = 0;

-	if (!dev || !dev->enabled) {
-		/* Skip IGD initialization in FSP if device is disabled in devicetree.cb. */
+	if (CONFIG(SOC_INTEL_DISABLE_IGD) || !dev || !dev->enabled) {
+		/* Skip IGD initialization in FSP if device is disabled */
    	m_cfg->InternalGfx = 0;
    	m_cfg->IgdDvmt50PreAlloc = 0;
    } else {
diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c
index cd70807..7100232 100644
--- a/src/soc/intel/jasperlake/romstage/fsp_params.c
+++ b/src/soc/intel/jasperlake/romstage/fsp_params.c
@@ -22,7 +22,7 @@
     * Otherwise, skip IGD init in FSP.
     */
    dev = pcidev_path_on_root(SA_DEVFN_IGD);
-	m_cfg->InternalGfx = is_dev_enabled(dev);
+	m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_dev_enabled(dev);
    m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 0xFE : 0;

m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
diff --git a/src/soc/intel/skylake/romstage/fsp_params.c b/src/soc/intel/skylake/romstage/fsp_params.c
index 2793c2d..6c6e2e6 100644
--- a/src/soc/intel/skylake/romstage/fsp_params.c
+++ b/src/soc/intel/skylake/romstage/fsp_params.c
@@ -112,7 +112,7 @@
    const struct device *dev;

dev = pcidev_path_on_root(SA_DEVFN_IGD);
-	m_cfg->InternalGfx = dev && dev->enabled;
+	m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && dev && dev->enabled;

/*
     * If iGPU is enabled, set IGD stolen size to 64MB. The FBC