[coreboot-gerrit] Patch set updated for coreboot: a91f91e AMD fam10: Move the test for connected HyperTransport link

[Kyösti Mälkki]

Kyösti Mälkki ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8350

-gerrit

commit a91f91e4a4f292be7df406b3606c1b5870aa22af
Author: Kyösti Mälkki 
Date:   Wed Feb 4 15:23:03 2015 +0200

AMD fam10: Move the test for connected HyperTransport link

Change-Id: I9a24f9897115ce37ee11ca41c8b74142c95fc534
    Signed-off-by: Kyösti Mälkki 
---
 src/northbridge/amd/amdfam10/northbridge.c | 32 +++++++++++++++++++-----------
 1 file changed, 20 insertions(+), 12 deletions(-)

diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 275c79c..f2b18d0 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -140,13 +140,29 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn)

}

+static bool is_non_coherent_link(struct device *dev, struct bus *link)
+{
+	u32 link_type;
+	do {
+		link_type = pci_read_config32(dev, link->cap + 0x18);
+	} while (link_type & ConnectionPending);
+
+	if (!(link_type & LinkConnected))
+		return false;
+
+	do {
+		link_type = pci_read_config32(dev, link->cap + 0x18);
+	} while (!(link_type & InitComplete));
+
+	return !!(link_type & NonCoherent);
+}
+
 static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_sblink,
    			u32 max)
 {
 //	I want to put sb chain in bus 0 can I?

-		u32 link_type;
    	int i;
    	u32 ht_c_index;
    	u32 ht_unitid_base[4]; // here assume only 4 HT device on chain
@@ -171,19 +187,11 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool
    		devx = dev;
    	}

+		/* Check for connected link. */
    	link->cap = 0x80 + ((link->link_num & 3) * 0x20);
-		do {
-			link_type = pci_read_config32(devx, link->cap + 0x18);
-		} while(link_type & ConnectionPending);
-		if (!(link_type & LinkConnected)) {
-			return max;
-		}
-		do {
-			link_type = pci_read_config32(devx, link->cap + 0x18);
-		} while(!(link_type & InitComplete));
-		if (!(link_type & NonCoherent)) {
+		if (!is_non_coherent_link(devx, link))
    		return max;
-		}
+
    	/* See if there is an available configuration space mapping
    	 * register in function 1.
    	 */