Hello build bot (Jenkins), Furquan Shaikh, Aaron Durbin, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42088
to look at the new patch set (#4).
Change subject: soc/amd/picasso: Write EIP to secure S3 ......................................................................
soc/amd/picasso: Write EIP to secure S3
This change is required so we have a defined entry point on S3. Without this, the S3_RESUME_EIP_MSR register could in theory be written to later which would be a security risk.
The PSP is responsible for loading bootblock into RAM. The bootblock image currently has a zeroed out BSS section. So when the image is loaded into RAM by the PSP we know that BSS is zero. On S3 resume, the PSP does not currently reload bootblock into RAM. This means that the previous BSS values will still be present. This violates the assumptions the program makes about global variables. So we need to explicitly clear it. The bss clearing code was copied from assembly_entry.S.
Until the PSP always reloads the bootblock, there is a risk of the OS modifying the bootblock. One we can switch to a new PSP version we can remove the BSS clearing code.
BUG=b:147042464 TEST=Resume trembyle and see bootblock start.
coreboot-4.12-512-g65779ebcf73f-dirty Thu Jun 4 22:38:17 UTC 2020 smm starting (log level: 8)...
SMI# #6 SMI#: SLP = 0x0c01 Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: Set SCI mask to 0x0000000000000000 Clearing pending EC events. Error code EC_RES_UNAVAILABLE(9) is expected. EC returned error result code 9 SMI#: Entering S3 (Suspend-To-RAM) PSP: Prepare to enter sleep state 3... OK SMU: Put system into S3/S4/S5 Timestamp - start of bootblock: 18446744070740509170
coreboot-4.12-512-g65779ebcf73f-dirty Thu Jun 4 22:38:17 UTC 2020 bootblock starting (log level: 8)... Family_Model: 00810f81 PMxC0 STATUS: 0x200800 SleepReset BIT11 I2C bus 3 version 0x3132322a DW I2C bus 3 at 0xfedc5000 (400 KHz) Timestamp - end of bootblock: 18446744070804450274 VBOOT: Loading verstage. FMAP: area COREBOOT found @ c75000 (3715072 bytes) CBFS: Locating 'fallback/verstage' CBFS: Found @ offset 61b80 size cee4 PROG_RUN: Setting MTRR to cache stage. base: 0x04000000, size: 0x00010000
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: I4b0b0d0d576fc42b1628a4547a5c9a10bcbe9d37 --- M src/soc/amd/picasso/bootblock/bootblock.c M src/soc/amd/picasso/bootblock/pre_c.S A src/soc/amd/picasso/include/soc/msr.h 3 files changed, 50 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/42088/4