[coreboot-gerrit] New patch to review for coreboot: mainboard/gigabyte/ga-b75m-d3h: Use tabs for indents

[HAOUAS Elyes]

HAOUAS Elyes ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16819

-gerrit

commit b5d7a0b7cacc247e72febd75920fac6217ed769c
Author: Elyes HAOUAS 
Date:   Thu Sep 29 20:21:28 2016 +0200

mainboard/gigabyte/ga-b75m-d3h: Use tabs for indents

Change-Id: I038e5cea654d1760ddb2c403c651d8f75e021251
    Signed-off-by: Elyes HAOUAS 
---
 src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c | 60 +++++++++++++-------------
 src/mainboard/gigabyte/ga-b75m-d3h/romstage.c  | 42 +++++++++---------
 2 files changed, 51 insertions(+), 51 deletions(-)

diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c
index 584fec0..7b1c506 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c
@@ -37,36 +37,36 @@ static void mainboard_init(device_t dev)
    RCBA32(0x38c8) = 0x00002005;
    RCBA32(0x38c4) = 0x00802005;
    RCBA32(0x38c0) = 0x00000007;
-        RCBA32(0x2240) = 0x00330e71;
-        RCBA32(0x2244) = 0x003f0eb1;
-        RCBA32(0x2248) = 0x002102cd;
-        RCBA32(0x224c) = 0x00f60000;
-        RCBA32(0x2250) = 0x00020000;
-        RCBA32(0x2254) = 0x00e3004c;
-        RCBA32(0x2258) = 0x00e20bef;
-        RCBA32(0x2260) = 0x003304ed;
-        RCBA32(0x2278) = 0x001107c1;
-        RCBA32(0x227c) = 0x001d07e9;
-        RCBA32(0x2280) = 0x00e20000;
-        RCBA32(0x2284) = 0x00ee0000;
-        RCBA32(0x2288) = 0x005b05d3;
-        RCBA32(0x2318) = 0x04b8ff2e;
-        RCBA32(0x231c) = 0x03930f2e;
-        RCBA32(0x3808) = 0x005044a3;
-        RCBA32(0x3810) = 0x52410000;
-        RCBA32(0x3814) = 0x0000008a;
-        RCBA32(0x3818) = 0x00000006;
-        RCBA32(0x381c) = 0x0000072e;
-        RCBA32(0x3820) = 0x0000000a;
-        RCBA32(0x3824) = 0x00000123;
-        RCBA32(0x3828) = 0x00000009;
-        RCBA32(0x382c) = 0x00000001;
-        RCBA32(0x3834) = 0x0000061a;
-        RCBA32(0x3838) = 0x00000003;
-        RCBA32(0x383c) = 0x00000a76;
-        RCBA32(0x3840) = 0x00000004;
-        RCBA32(0x3844) = 0x0000e5e4;
-        RCBA32(0x3848) = 0x0000000e;
+	RCBA32(0x2240) = 0x00330e71;
+	RCBA32(0x2244) = 0x003f0eb1;
+	RCBA32(0x2248) = 0x002102cd;
+	RCBA32(0x224c) = 0x00f60000;
+	RCBA32(0x2250) = 0x00020000;
+	RCBA32(0x2254) = 0x00e3004c;
+	RCBA32(0x2258) = 0x00e20bef;
+	RCBA32(0x2260) = 0x003304ed;
+	RCBA32(0x2278) = 0x001107c1;
+	RCBA32(0x227c) = 0x001d07e9;
+	RCBA32(0x2280) = 0x00e20000;
+	RCBA32(0x2284) = 0x00ee0000;
+	RCBA32(0x2288) = 0x005b05d3;
+	RCBA32(0x2318) = 0x04b8ff2e;
+	RCBA32(0x231c) = 0x03930f2e;
+	RCBA32(0x3808) = 0x005044a3;
+	RCBA32(0x3810) = 0x52410000;
+	RCBA32(0x3814) = 0x0000008a;
+	RCBA32(0x3818) = 0x00000006;
+	RCBA32(0x381c) = 0x0000072e;
+	RCBA32(0x3820) = 0x0000000a;
+	RCBA32(0x3824) = 0x00000123;
+	RCBA32(0x3828) = 0x00000009;
+	RCBA32(0x382c) = 0x00000001;
+	RCBA32(0x3834) = 0x0000061a;
+	RCBA32(0x3838) = 0x00000003;
+	RCBA32(0x383c) = 0x00000a76;
+	RCBA32(0x3840) = 0x00000004;
+	RCBA32(0x3844) = 0x0000e5e4;
+	RCBA32(0x3848) = 0x0000000e;
 }

// mainboard_enable is executed as first thing after
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
index dd889d1..06fee7e 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
@@ -150,10 +150,10 @@ void pch_enable_lpc(void)
    pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
    		CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);

-        pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01);
-        pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
+	pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01);
+	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);

-        pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000);
+	pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000);

/* Initialize SuperIO */
    ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
@@ -161,27 +161,27 @@ void pch_enable_lpc(void)
 }

const struct southbridge_usb_port mainboard_usb_ports[] = {
-        { 1, 5, 0 },
-        { 1, 5, 0 },
-        { 1, 5, 1 },
-        { 1, 5, 1 },
-        { 1, 5, 2 },
-        { 1, 5, 2 },
-        { 1, 5, 3 },
-        { 1, 5, 3 },
-        { 1, 5, 4 },
-        { 1, 5, 4 },
-        { 1, 5, 6 },
-        { 1, 5, 5 },
-        { 1, 5, 5 },
-        { 1, 5, 6 },
+	{ 1, 5, 0 },
+	{ 1, 5, 0 },
+	{ 1, 5, 1 },
+	{ 1, 5, 1 },
+	{ 1, 5, 2 },
+	{ 1, 5, 2 },
+	{ 1, 5, 3 },
+	{ 1, 5, 3 },
+	{ 1, 5, 4 },
+	{ 1, 5, 4 },
+	{ 1, 5, 6 },
+	{ 1, 5, 5 },
+	{ 1, 5, 5 },
+	{ 1, 5, 6 },
 };

void mainboard_get_spd(spd_raw_data *spd) {
-        read_spd (&spd[0], 0x50);
-        read_spd (&spd[1], 0x51);
-        read_spd (&spd[2], 0x52);
-        read_spd (&spd[3], 0x53);
+	read_spd (&spd[0], 0x50);
+	read_spd (&spd[1], 0x51);
+	read_spd (&spd[2], 0x52);
+	read_spd (&spd[3], 0x53);
 }

#if 0