Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78085?usp=email )
Change subject: soc/intel: Move USB wake methods to a common ASL file ......................................................................
soc/intel: Move USB wake methods to a common ASL file
The ACPI methods for enabling USB wake are identical on ADL, CNL and SKL. Move them to a common ASL file so they can be reused more easily on other SoCs.
Also move the USB_PORT_WAKE_ENABLE macro used to create enable bitmasks in devicetree to a common header.
BUG=b:300844110 TEST=Use abuild to build kinox, puff, and fizz with and without this change. Check the generated dsdt.aml is unchanged.
Change-Id: Iabdfe2bece7fafc284ddf04382f1bbcacc370cce Signed-off-by: Reka Norman rekanorman@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/78085 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Martin L Roth gaumless@gmail.com --- M src/soc/intel/alderlake/acpi/xhci.asl M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/include/soc/usb.h M src/soc/intel/cannonlake/acpi/xhci.asl M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/include/soc/usb.h A src/soc/intel/common/acpi/xhci_wake.asl M src/soc/intel/common/block/include/intelblocks/xhci.h M src/soc/intel/skylake/acpi/xhci.asl M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/include/soc/usb.h 11 files changed, 65 insertions(+), 156 deletions(-)
Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved
diff --git a/src/soc/intel/alderlake/acpi/xhci.asl b/src/soc/intel/alderlake/acpi/xhci.asl index e4001fe..1c3bbbe 100644 --- a/src/soc/intel/alderlake/acpi/xhci.asl +++ b/src/soc/intel/alderlake/acpi/xhci.asl @@ -3,51 +3,8 @@ #include <intelblocks/xhci.h> #include <soc/gpe.h>
-/* - * USB Port Wake Enable (UPWE) on usb attach/detach - * Arg0 - Port Number - * Arg1 - Port 1 Status and control offset - * Arg2 - xHCI Memory-mapped address - */ -Method (UPWE, 3, Serialized) -{ - Local0 = Arg1 + ((Arg0 - 1) * 0x10) - - /* Map ((XMEM << 16) + Local0 in PSCR */ - OperationRegion (PSCR, SystemMemory, (Arg2 << 16) + Local0, 0x10) - Field (PSCR, DWordAcc, NoLock, Preserve) - { - PSCT, 32, - } - Local0 = PSCT - Local0 &= PORTSCN_BITS_OFF_MASK - Local0 |= PORTSCN_WAKE_ON_BOTH_CONNECT_DISCONNECT_ENABLE - PSCT = Local0 -} - -/* - * USB Wake Enable Setup (UWES) - * Arg0 - Port enable bitmap - * Arg1 - Port 1 Status and control offset - * Arg2 - xHCI Memory-mapped address - */ -Method (UWES, 3, Serialized) -{ - Local0 = Arg0 - - While (1) { - FindSetRightBit (Local0, Local1) - If (Local1 == 0) { - Break - } - UPWE (Local1, Arg1, Arg2) - /* - * Clear the lowest set bit in Local0 since it was - * processed. - */ - Local0 &= (Local0 - 1) - } -} +/* Include UWES method for enabling USB wake */ +#include <soc/intel/common/acpi/xhci_wake.asl>
/* XHCI Controller 0:14.0 */
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 65d6e85..b1e90fa 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -12,6 +12,7 @@ #include <intelblocks/power_limit.h> #include <intelblocks/pcie_rp.h> #include <intelblocks/tcss.h> +#include <intelblocks/xhci.h> #include <soc/gpe.h> #include <soc/pci_devs.h> #include <soc/pmc.h> diff --git a/src/soc/intel/alderlake/include/soc/usb.h b/src/soc/intel/alderlake/include/soc/usb.h index 2a701c8..b84cce7 100644 --- a/src/soc/intel/alderlake/include/soc/usb.h +++ b/src/soc/intel/alderlake/include/soc/usb.h @@ -163,11 +163,4 @@ .ocpin = (pin), \ }
-/* - * Set bit corresponding to USB port in wake enable bitmap. Bit 0 corresponds - * to Port 1, Bit n corresponds to Port (n+1). This bitmap is later used to - * decide what ports need to set PORTSCN/PORTSCXUSB3 register bits. - */ -#define USB_PORT_WAKE_ENABLE(x) (1 << ((x) - 1)) - #endif diff --git a/src/soc/intel/cannonlake/acpi/xhci.asl b/src/soc/intel/cannonlake/acpi/xhci.asl index 0f8f51f..beaa843 100644 --- a/src/soc/intel/cannonlake/acpi/xhci.asl +++ b/src/soc/intel/cannonlake/acpi/xhci.asl @@ -3,51 +3,8 @@ #include <intelblocks/xhci.h> #include <soc/gpe.h>
-/* - * USB Port Wake Enable (UPWE) on usb attach/detach - * Arg0 - Port Number - * Arg1 - Port 1 Status and control offset - * Arg2 - xHCI Memory-mapped address - */ -Method (UPWE, 3, Serialized) -{ - Local0 = Arg1 + ((Arg0 - 1) * 0x10) - - /* Map ((XMEM << 16) + Local0 in PSCR */ - OperationRegion (PSCR, SystemMemory, (Arg2 << 16) + Local0, 0x10) - Field (PSCR, DWordAcc, NoLock, Preserve) - { - PSCT, 32, - } - Local0 = PSCT - Local0 = Local0 & PORTSCN_BITS_OFF_MASK - Local0 = Local0 | PORTSCN_WAKE_ON_BOTH_CONNECT_DISCONNECT_ENABLE - PSCT = Local0 -} - -/* - * USB Wake Enable Setup (UWES) - * Arg0 - Port enable bitmap - * Arg1 - Port 1 Status and control offset - * Arg2 - xHCI Memory-mapped address - */ -Method (UWES, 3, Serialized) -{ - Local0 = Arg0 - - While (1) { - FindSetRightBit (Local0, Local1) - If (Local1 == 0) { - Break - } - UPWE (Local1, Arg1, Arg2) - /* - * Clear the lowest set bit in Local0 since it was - * processed. - */ - Local0 = Local0 & (Local0 - 1) - } -} +/* Include UWES method for enabling USB wake */ +#include <soc/intel/common/acpi/xhci_wake.asl>
/* XHCI Controller 0:14.0 */
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 3093050..994f2ae 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -10,6 +10,7 @@ #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/power_limit.h> +#include <intelblocks/xhci.h> #include <stdbool.h> #include <stdint.h> #include <soc/pch.h> diff --git a/src/soc/intel/cannonlake/include/soc/usb.h b/src/soc/intel/cannonlake/include/soc/usb.h index 20b3149..3f020ef 100644 --- a/src/soc/intel/cannonlake/include/soc/usb.h +++ b/src/soc/intel/cannonlake/include/soc/usb.h @@ -186,11 +186,4 @@ .gen2_rx_filter_sel = 0x44, \ }
-/* - * Set bit corresponding to USB port in wake enable bitmap. Bit 0 corresponds - * to Port 1, Bit n corresponds to Port (n+1). This bitmap is later used to - * decide what ports need to set PORTSCN/PORTSCXUSB3 register bits. - */ -#define USB_PORT_WAKE_ENABLE(x) (1 << ((x) - 1)) - #endif diff --git a/src/soc/intel/common/acpi/xhci_wake.asl b/src/soc/intel/common/acpi/xhci_wake.asl new file mode 100644 index 0000000..e029a6f --- /dev/null +++ b/src/soc/intel/common/acpi/xhci_wake.asl @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/xhci.h> + +/* + * USB Port Wake Enable (UPWE) on usb attach/detach + * Arg0 - Port Number + * Arg1 - Port 1 Status and control offset + * Arg2 - xHCI Memory-mapped address + */ +Method (UPWE, 3, Serialized) +{ + Local0 = Arg1 + ((Arg0 - 1) * 0x10) + + /* Map ((XMEM << 16) + Local0 in PSCR */ + OperationRegion (PSCR, SystemMemory, (Arg2 << 16) + Local0, 0x10) + Field (PSCR, DWordAcc, NoLock, Preserve) + { + PSCT, 32, + } + Local0 = PSCT + Local0 &= PORTSCN_BITS_OFF_MASK + Local0 |= PORTSCN_WAKE_ON_BOTH_CONNECT_DISCONNECT_ENABLE + PSCT = Local0 +} + +/* + * USB Wake Enable Setup (UWES) + * Arg0 - Port enable bitmap + * Arg1 - Port 1 Status and control offset + * Arg2 - xHCI Memory-mapped address + */ +Method (UWES, 3, Serialized) +{ + Local0 = Arg0 + + While (1) { + FindSetRightBit (Local0, Local1) + If (Local1 == 0) { + Break + } + UPWE (Local1, Arg1, Arg2) + /* + * Clear the lowest set bit in Local0 since it was + * processed. + */ + Local0 &= (Local0 - 1) + } +} diff --git a/src/soc/intel/common/block/include/intelblocks/xhci.h b/src/soc/intel/common/block/include/intelblocks/xhci.h index 15b16d2..1a72e0f 100644 --- a/src/soc/intel/common/block/include/intelblocks/xhci.h +++ b/src/soc/intel/common/block/include/intelblocks/xhci.h @@ -16,6 +16,13 @@ #define PORTSCN_BITS_OFF_MASK ~0x80FE0012 #define PORTSCXUSB3_OFFSET 0x540
+/* + * Set bit corresponding to USB port in wake enable bitmap. Bit 0 corresponds + * to Port 1, Bit n corresponds to Port (n+1). This bitmap is later used to + * decide what ports need to set PORTSCN/PORTSCXUSB3 register bits. + */ +#define USB_PORT_WAKE_ENABLE(x) (1 << ((x) - 1)) + #if !defined(__ACPI__) #include <device/device.h> #include <device/xhci.h> diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl index 0540919..bfe6c6d 100644 --- a/src/soc/intel/skylake/acpi/xhci.asl +++ b/src/soc/intel/skylake/acpi/xhci.asl @@ -2,51 +2,8 @@
#include <intelblocks/xhci.h>
-/* - * USB Port Wake Enable (UPWE) on usb attach/detach - * Arg0 - Port Number - * Arg1 - Port 1 Status and control offset - * Arg2 - xHCI Memory-mapped address - */ -Method (UPWE, 3, Serialized) -{ - Local0 = Arg1 + ((Arg0 - 1) * 0x10) - - /* Map ((XMEM << 16) + Local0 in PSCR */ - OperationRegion (PSCR, SystemMemory, (Arg2 << 16) + Local0, 0x10) - Field (PSCR, DWordAcc, NoLock, Preserve) - { - PSCT, 32, - } - Local0 = PSCT - Local0 = Local0 & PORTSCN_BITS_OFF_MASK - Local0 = Local0 | PORTSCN_WAKE_ON_BOTH_CONNECT_DISCONNECT_ENABLE - PSCT = Local0 -} - -/* - * USB Wake Enable Setup (UWES) - * Arg0 - Port enable bitmap - * Arg1 - Port 1 Status and control offset - * Arg2 - xHCI Memory-mapped address - */ -Method (UWES, 3, Serialized) -{ - Local0 = Arg0 - - While (1) { - FindSetRightBit (Local0, Local1) - If (Local1 == 0) { - Break - } - UPWE (Local1, Arg1, Arg2) - /* - * Clear the lowest set bit in Local0 since it was - * processed. - */ - Local0 = Local0 & (Local0 - 1) - } -} +/* Include UWES method for enabling USB wake */ +#include <soc/intel/common/acpi/xhci_wake.asl>
/* XHCI Controller 0:14.0 */
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 5119037..3070c46 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -12,6 +12,7 @@ #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/power_limit.h> +#include <intelblocks/xhci.h> #include <stdbool.h> #include <stdint.h> #include <soc/gpe.h> diff --git a/src/soc/intel/skylake/include/soc/usb.h b/src/soc/intel/skylake/include/soc/usb.h index 7912603..612ad5f 100644 --- a/src/soc/intel/skylake/include/soc/usb.h +++ b/src/soc/intel/skylake/include/soc/usb.h @@ -180,11 +180,4 @@ .tx_downscale_amp = 0x00, \ }
-/* - * Set bit corresponding to USB port in wake enable bitmap. Bit 0 corresponds - * to Port 1, Bit n corresponds to Port (n+1). This bitmap is later used to - * decide what ports need to set PORTSCN/PORTSCXUSB3 register bits. - */ -#define USB_PORT_WAKE_ENABLE(x) (1 << ((x) - 1)) - #endif