Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35902 )
Change subject: soc/intel/apl,skl,cnl,icl: implement a PRMRR size selection algorithm ......................................................................
Patch Set 8:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35902/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35902/7//COMMIT_MSG@34 PS7, Line 34: Todo: needs testing
I'm rather sure the alignment is 256MiB for newer SoCs. Maybe Kaby Lake is the exception, though, and really aligns to 128MiB.
For me it seems the maximum possible value is used for alignedment. KBL does not support 256, so aligment happens to 128. Not sure for the previous platforms, though.
Do you mean KBL or its FSP doesn't support 256MiB? The former seems to support it. At least IIRC, you reported a 0x1e0 for your MSR reading? Wasn't that KBL?
If the CPU supports it, there's a 50% chance that we can test the latter. Just set it to 256MiB and see where it is aligned (if 128/256MiB align- ment would mean the same, that says nothing, though).
https://review.coreboot.org/c/coreboot/+/35902/8/src/soc/intel/common/block/... File src/soc/intel/common/block/cpu/cpulib.c:
https://review.coreboot.org/c/coreboot/+/35902/8/src/soc/intel/common/block/... PS8, Line 346: valid_size
limit will be used to set the maximum size later in Kconfig, see sgx Kconfig commit. […]
I meant you use the wrong variable. The text says unsupported limit, you output constant 0 (in form of the variable `valid_size`).