Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38296 )
Change subject: intel/{i945,pineview},i82801gx: Move enable_smbus() call ......................................................................
intel/{i945,pineview},i82801gx: Move enable_smbus() call
Change-Id: I7a9e613f9a142e04030672f85ea80c56151be3c5 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/northbridge/intel/i945/romstage.c M src/northbridge/intel/pineview/romstage.c M src/southbridge/intel/i82801gx/early_init.c 3 files changed, 3 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/38296/1
diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c index 4795881..ff4ccc1 100644 --- a/src/northbridge/intel/i945/romstage.c +++ b/src/northbridge/intel/i945/romstage.c @@ -61,9 +61,6 @@
s3resume = southbridge_detect_s3_resume();
- /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - mainboard_pre_raminit_config(s3resume);
if (CONFIG(DEBUG_RAM_SETUP)) diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index e324c05..ce4cd55 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -51,8 +51,6 @@
enable_lapic();
- enable_smbus(); - /* Perform some early chipset initialization required * before RAM initialization can work */ diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index f91a5dc..29c4550 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -73,6 +73,9 @@ { uint8_t reg8; uint32_t reg32; + + enable_smbus(); + /* Setting up Southbridge. In the northbridge code. */ printk(BIOS_DEBUG, "Setting up static southbridge registers..."); i82801gx_setup_bars();