Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35537 )
Change subject: sb/intel/spi: Use different SPIOPS for some SST flashes ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35537/2/src/southbridge/intel/commo... File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/c/coreboot/+/35537/2/src/southbridge/intel/commo... PS2, Line 1056: : const char *(aai_write_flash[]) = { : "SST25VF040B", : "SST25VF080B", : "SST25VF080", : "SST25VF016B", : "SST25VF032B", : "SST25WF512", : "SST25WF010", : "SST25WF020", : "SST25WF040", : "SST25WF080", : "SST25WF080B" : }; Except id_code 0x4b all others use AAI_WRITE. Should that be checked for? amd/soc does it like that.