[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso/soc_util: add comment on the silicon and soc types

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42838 )

Change subject: soc/amd/picasso/soc_util: add comment on the silicon and soc types
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soc/amd/picasso/soc_util: add comment on the silicon and soc types

Change-Id: I71704ab292edf8bd343370e6b72c47a8f3aceffd
Signed-off-by: Felix Held 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42838
Tested-by: build bot (Jenkins) 
Reviewed-by: Raul Rangel 
Reviewed-by: Angel Pons 
---
M src/soc/amd/picasso/soc_util.c
1 file changed, 8 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Raul Rangel: Looks good to me, approved
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/amd/picasso/soc_util.c b/src/soc/amd/picasso/soc_util.c
index 64a97a0..1212920 100644
--- a/src/soc/amd/picasso/soc_util.c
+++ b/src/soc/amd/picasso/soc_util.c
@@ -9,6 +9,14 @@
 #include <soc/soc_util.h>
 #include <types.h>

+/*
+ * The Zen/Zen+ based APUs can be RV (sometimes called RV1), PCO or RV2 silicon. RV2 has less
+ * PCIe, USB3 and DisplayPort connectivity than RV(1) or PCO. A Picasso SoC is always PCO
+ * silicon, a Dali SoC can either be RV2 or fused-down PCO silicon that has the same
+ * connectivity as the RV2 one and Pollock is always RV2 silicon. Picasso and Dali are in a FP5
+ * package while Pollock is in the smaller FT5 package.
+ */
+
 #define SOCKET_TYPE_SHIFT	28
 #define SOCKET_TYPSE_MASK	(0xf << SOCKET_TYPE_SHIFT)