Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49171 )
Change subject: [UNTESTED] sb/intel/bd82x6x: Handle root port lane mapping ......................................................................
[UNTESTED] sb/intel/bd82x6x: Handle root port lane mapping
PCH PCIe lane-to-port mapping can be configured through IFD straps. Depending on the strapped port widths, some registers need to be programmed differently. The same logic applies to the two groups of four lanes/ports, but the register offsets are different.
Change-Id: Icb8b8280ab51c736417f202fc30d6ab486b388a8 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/bd82x6x/early_pch.c 1 file changed, 35 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/49171/1
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index f684a96..903dc01 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -135,6 +135,40 @@ ; }
+static void pch_assign_pcie_lane_mapping(void) +{ + const u32 rpc = RCBA32(RPC); + + for (unsigned int group = 0; group < 2; group++) { + + const u32 group_base = 0xec000403 + 0x400 * group; + + const unsigned int group_offset = 22 - 2 * group; + + switch (rpc >> (2 * group) & 3) { + case 3: /* x4 */ + RCBA32_AND_OR(0x2310, ~(3 << group_offset), 2 << group_offset); + + pch_iobp_update(group_base + 0x100, ~(0x1f << 27), (1 << 2 | 1) << 27); + pch_iobp_update(group_base + 0x200, ~(0x1f << 27), (2 << 2 | 1) << 27); + pch_iobp_update(group_base + 0x300, ~(0x1f << 27), (3 << 2 | 1) << 27); + break; + + case 2: /* x2, x2 */ + RCBA32_AND_OR(0x2310, ~(3 << group_offset), 1 << group_offset); + + pch_iobp_update(group_base + 0x100, ~(0x1f << 27), (1 << 2 | 1) << 27); + pch_iobp_update(group_base + 0x300, ~(0x1f << 27), (1 << 2 | 1) << 27); + break; + + case 1: /* x2, x1, x1 */ + case 0: /* x1, x1, x1, x1 */ + default: + RCBA32_AND_OR(0x2310, ~(3 << group_offset), 0); + } + } +} + void early_pch_init_native(void) { /* Lock down PMBASE */ @@ -148,10 +182,7 @@ RCBA32_AND_OR(0x2310, ~(3 << 29), 1 << 29); RCBA32(DMC2) = 0x00854c74;
- /* TODO: Handle non-zero cases */ - RCBA8(RPC); - RCBA32_AND_OR(0x2310, ~(3 << 22), 0); - RCBA32_AND_OR(0x2310, ~(3 << 20), 0); + pch_assign_pcie_lane_mapping();
write_iobp(0xea007f62, 0x00590133); write_iobp(0xec007f62, 0x00590133);