[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Fix FSP UPDs settings with disabled GBE

[Kane Chen (Code Review)]

Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35595 )

Change subject: soc/intel/cannonlake: Fix FSP UPDs settings with disabled GBE
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Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35595/2/src/soc/intel/cannonlake/fs... 
File src/soc/intel/cannonlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/35595/2/src/soc/intel/cannonlake/fs... 
PS2, Line 207: && params->PchLanEnable
> Aah I see in a follow up CL, you are actually using the Vm settings. […]

Hi Furquan,
I think it's due to PchPmSlpS0VmSupports UPDs will enable some clk gating settings in CPPM hence it would make slps0 gbe not working.

The PchPmSlpS0VmSupport UPDs are used to tell FSP that HW design can support VCCPRIM_CORE Low Voltage Mode so that certain power gating settings can be enabled.

For more details, we can go back to issue tracker to discussed

Thanks