[coreboot-gerrit] [M] Change in coreboot[main]: soc/intel/xeon_sp: Add IIO resources via SSDT

[Arthur Heymans (Code Review)]

Attention is currently required from: Christian Walter, Felix Held, Johnny Lin, Nico Huber, Shuo Liu, Tim Chu.

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78333?usp=email )

Change subject: soc/intel/xeon_sp: Add IIO resources via SSDT
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Patch Set 16:

(1 comment)

File src/soc/intel/xeon_sp/spr/soc_acpi.c:

https://review.coreboot.org/c/coreboot/+/78333/comment/31166058_1dea2dac :
PS12, Line 382: 				create_dsdt_iou_cxl_resource(socket, stack, ri, stack_enabled);
> for SPR, stack0 of each socket (8 lanes) cannot support CXL card (16 lanes) physically, hence is_iio_cxl_stack_res(ri) will always be false for stack0.

This would be a functional change? Maybe split that off to a different commit?