Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41943 )
Change subject: sb/intel/lynxpoint: Clean up code ......................................................................
sb/intel/lynxpoint: Clean up code
Fix code and comment style, reflow lines and constify a few things.
Tested with abuild --timeless with asrock/b85m_pro4 and google/slippy.
Change-Id: Idb908d1a610c10897e1005ba024e433979347fa6 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/lynxpoint/acpi.c M src/southbridge/intel/lynxpoint/azalia.c M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/chip.h M src/southbridge/intel/lynxpoint/early_me.c M src/southbridge/intel/lynxpoint/early_usb.c M src/southbridge/intel/lynxpoint/elog.c M src/southbridge/intel/lynxpoint/hda_verb.c M src/southbridge/intel/lynxpoint/lp_gpio.c M src/southbridge/intel/lynxpoint/lp_gpio.h M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/me.h M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/me_status.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/pcie.c M src/southbridge/intel/lynxpoint/pmutil.c M src/southbridge/intel/lynxpoint/rcba.c M src/southbridge/intel/lynxpoint/sata.c M src/southbridge/intel/lynxpoint/serialio.c M src/southbridge/intel/lynxpoint/smbus.c M src/southbridge/intel/lynxpoint/smi.c M src/southbridge/intel/lynxpoint/smihandler.c M src/southbridge/intel/lynxpoint/usb_ehci.c M src/southbridge/intel/lynxpoint/usb_xhci.c 26 files changed, 353 insertions(+), 417 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/41943/1
diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index d63af6c..7569f90 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -37,8 +37,7 @@ hpet->number = 0x00; hpet->min_tick = 0x0080;
- header->checksum = - acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); + header->checksum = acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); }
static void acpi_create_serialio_ssdt_entry(int id, global_nvs_t *gnvs) diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index 4122dbb..73a931b 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -18,9 +18,7 @@ /* Can support up to 4 codecs */ for (i = 3; i >= 0; i--) { if (codec_mask & (1 << i)) - hda_codec_init(base, i, - cim_verb_data_size, - cim_verb_data); + hda_codec_init(base, i, cim_verb_data_size, cim_verb_data); }
if (pc_beep_verbs_size) @@ -53,8 +51,7 @@ pci_write_config32(dev, 0x114, reg32);
// Set VCi enable bit - if (pci_read_config32(dev, 0x120) & ((1 << 24) | - (1 << 25) | (1 << 26))) { + if (pci_read_config32(dev, 0x120) & ((1 << 24) | (1 << 25) | (1 << 26))) { reg32 = pci_read_config32(dev, 0x120); if (pch_is_lp()) reg32 &= ~(1UL << 31); @@ -138,7 +135,7 @@ }
static struct pci_operations azalia_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, };
static struct device_operations azalia_ops = { diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index b015ea2..0f59d70 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -31,7 +31,7 @@ static void enable_port80_on_lpc(void) { /* Enable port 80 POST on LPC. The chipset does this by default, - * but it doesn't appear to hurt anything. */ + but it doesn't appear to hurt anything. */ u32 gcs = RCBA32(GCS); gcs = gcs & ~0x4; RCBA32(GCS) = gcs; diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index ed362a2..fa87048 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -105,4 +105,4 @@ };
-#endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H */ +#endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H */ diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c index e5ce3f5..c1503eb 100644 --- a/src/southbridge/intel/lynxpoint/early_me.c +++ b/src/southbridge/intel/lynxpoint/early_me.c @@ -125,10 +125,7 @@
pci_write_dword_ptr(&did, PCI_ME_H_GS);
- /* - * The ME firmware does not respond with an ACK when NOMEM or ERROR - * are sent. - */ + /* The ME firmware does not respond with an ACK when NOMEM or ERROR are sent. */ if (status == ME_INIT_STATUS_NOMEM || status == ME_INIT_STATUS_ERROR) return 0;
diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c index 06ddd08..86abbe0 100644 --- a/src/southbridge/intel/lynxpoint/early_usb.c +++ b/src/southbridge/intel/lynxpoint/early_usb.c @@ -4,7 +4,8 @@ #include <device/pci_def.h> #include "pch.h"
-/* HCD_INDEX == 2 selects 0:1a.0 (PCH_EHCI2), any other index +/* + * HCD_INDEX == 2 selects 0:1a.0 (PCH_EHCI2), any other index * selects 0:1d.0 (PCH_EHCI1) for usbdebug use. */ #if CONFIG_USBDEBUG_HCD_INDEX != 2 @@ -16,11 +17,9 @@ #endif
/* - * Setup USB controller MMIO BAR to prevent the - * reference code from resetting the controller. + * Setup USB controller MMIO BAR to prevent the reference code from resetting the controller. * - * The BAR will be re-assigned during device - * enumeration so these are only temporary. + * The BAR will be re-assigned during device enumeration so these are only temporary. */ static void enable_usb_bar_on_device(pci_devfn_t dev, u32 bar) { diff --git a/src/southbridge/intel/lynxpoint/elog.c b/src/southbridge/intel/lynxpoint/elog.c index 2e4df72..d8fadf9 100644 --- a/src/southbridge/intel/lynxpoint/elog.c +++ b/src/southbridge/intel/lynxpoint/elog.c @@ -30,7 +30,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts_reg, u32 gpe0_en_reg, int start) { /* GPE Bank 1 is GPIO 0-31 */ - u32 gpe0_en = inl(get_pmbase() + gpe0_en_reg); + u32 gpe0_en = inl(get_pmbase() + gpe0_en_reg); u32 gpe0_sts = inl(get_pmbase() + gpe0_sts_reg) & gpe0_en; int i;
@@ -46,7 +46,7 @@ u16 pmbase = get_pmbase(); u32 gpe0_sts, gpe0_en; int gpe0_high_gpios[] = { - [0] = 27, + [0] = 27, [24] = 17, [25] = 19, [26] = 21, @@ -60,26 +60,23 @@ pch_log_standard_gpe(GPE0_EN, GPE0_STS);
/* GPIO 0-15 */ - gpe0_en = inw(pmbase + GPE0_EN + 2); + gpe0_en = inw(pmbase + GPE0_EN + 2); gpe0_sts = inw(pmbase + GPE0_STS + 2) & gpe0_en; + for (i = 0; i <= 15; i++) { if (gpe0_sts & (1 << i)) elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i); }
- /* - * Now check and log upper status bits - */ - - gpe0_en = inl(pmbase + GPE0_EN_2); + /* Now check and log upper status bits */ + gpe0_en = inl(pmbase + GPE0_EN_2); gpe0_sts = inl(pmbase + GPE0_STS_2) & gpe0_en;
for (i = 0; i <= 31; i++) { if (!gpe0_high_gpios[i]) continue; if (gpe0_sts & (1 << i)) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, - gpe0_high_gpios[i]); + elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, gpe0_high_gpios[i]); } }
@@ -102,9 +99,9 @@ if (!lpc) return;
- pm1_sts = inw(get_pmbase() + PM1_STS); + pm1_sts = inw(get_pmbase() + PM1_STS); tco2_sts = inw(get_pmbase() + TCO2_STS); - gen_pmcon_2 = pci_read_config8(lpc, GEN_PMCON_2); + gen_pmcon_2 = pci_read_config8(lpc, GEN_PMCON_2); gen_pmcon_3 = pci_read_config16(lpc, GEN_PMCON_3);
/* PWR_FLR Power Failure */ @@ -141,8 +138,7 @@
/* ACPI Wake */ if (pm1_sts & (1 << 15)) - elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, - acpi_is_wakeup_s3() ? 3 : 5); + elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, acpi_is_wakeup_s3() ? 3 : 5);
/* * Wake sources diff --git a/src/southbridge/intel/lynxpoint/hda_verb.c b/src/southbridge/intel/lynxpoint/hda_verb.c index 9d264e0..59f6028 100644 --- a/src/southbridge/intel/lynxpoint/hda_verb.c +++ b/src/southbridge/intel/lynxpoint/hda_verb.c @@ -69,14 +69,12 @@ }
/** - * Wait 50usec for the codec to indicate it is ready - * no response would imply that the codec is non-operative + * Wait 50usec for the codec to indicate it is ready. + * No response would imply that the codec is non-operative. */ static int hda_wait_for_ready(u8 *base) { - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ - + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ int timeout = 50;
while (timeout--) { @@ -90,9 +88,8 @@ }
/** - * Wait 50usec for the codec to indicate that it accepted - * the previous command. No response would imply that the code - * is non-operative + * Wait 50usec for the codec to indicate that it accepted the previous command. + * No response would imply that the codec is non-operative. */ static int hda_wait_for_valid(u8 *base) { @@ -103,14 +100,12 @@ reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; write32(base + HDA_ICII_REG, reg32);
- /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ - + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ int timeout = 50; + while (timeout--) { reg32 = read32(base + HDA_ICII_REG); - if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == - HDA_ICII_VALID) + if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) return 0; udelay(1); } @@ -143,19 +138,18 @@ * 2 - Subsystem ID * 3 - Number of jacks (groups of 4 dwords) for this codec */ -static u32 hda_find_verb(u32 verb_table_bytes, - const u32 *verb_table_data, - u32 viddid, const u32 **verb) +static u32 hda_find_verb(u32 verb_table_bytes, const u32 *verb_table_data, u32 viddid, + const u32 **verb) { - int idx=0; + int idx = 0;
while (idx < (verb_table_bytes / sizeof(u32))) { - u32 verb_size = 4 * verb_table_data[idx+2]; // in u32 + u32 verb_size = 4 * verb_table_data[idx + 2]; // in u32 if (verb_table_data[idx] != viddid) { idx += verb_size + 3; // skip verb + header continue; } - *verb = &verb_table_data[idx+3]; + *verb = &verb_table_data[idx + 3]; return verb_size; }
diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c index c85ba2c..6599a43 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.c +++ b/src/southbridge/intel/lynxpoint/lp_gpio.c @@ -14,12 +14,10 @@ #ifdef __SIMPLE_DEVICE__ return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; #else - return pci_read_config16(pcidev_on_root(0x1f, 0), - GPIO_BASE) & 0xfffc; + return pci_read_config16(pcidev_on_root(0x1f, 0), GPIO_BASE) & 0xfffc; #endif }
- /* * This function will return a number that indicates which PIRQ * this GPIO maps to. If this is not a PIRQ capable GPIO then @@ -28,16 +26,16 @@ static int lp_gpio_to_pirq(int gpio) { switch (gpio) { - case 8: return 0; /* PIRQI */ - case 9: return 1; /* PIRQJ */ - case 10: return 2; /* PIRQK */ - case 13: return 3; /* PIRQL */ - case 14: return 4; /* PIRQM */ - case 45: return 5; /* PIRQN */ - case 46: return 6; /* PIRQO */ - case 47: return 7; /* PIRQP */ - case 48: return 8; /* PIRQQ */ - case 49: return 9; /* PIRQR */ + case 8: return 0; /* PIRQI */ + case 9: return 1; /* PIRQJ */ + case 10: return 2; /* PIRQK */ + case 13: return 3; /* PIRQL */ + case 14: return 4; /* PIRQM */ + case 45: return 5; /* PIRQN */ + case 46: return 6; /* PIRQO */ + case 47: return 7; /* PIRQP */ + case 48: return 8; /* PIRQQ */ + case 49: return 9; /* PIRQR */ case 50: return 10; /* PIRQS */ case 51: return 11; /* PIRQT */ case 52: return 12; /* PIRQU */ @@ -50,7 +48,7 @@
void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[]) { - u16 gpio_base = get_gpio_base(); + const u16 gpio_base = get_gpio_base(); const struct pch_lp_gpio_map *config; u32 owner[3] = {0}; u32 route[3] = {0}; @@ -102,7 +100,7 @@
int get_gpio(int gpio_num) { - u16 gpio_base = get_gpio_base(); + const u16 gpio_base = get_gpio_base();
if (gpio_num > MAX_GPIO_NUMBER) return 0; @@ -111,7 +109,7 @@ }
/* - * get a number comprised of multiple GPIO values. gpio_num_array points to + * Get a number comprised of multiple GPIO values. gpio_num_array points to * the array of gpio pin numbers to scan, terminated by -1. */ unsigned int get_gpios(const int *gpio_num_array) @@ -131,7 +129,7 @@
void set_gpio(int gpio_num, int value) { - u16 gpio_base = get_gpio_base(); + const u16 gpio_base = get_gpio_base(); u32 conf0;
if (gpio_num > MAX_GPIO_NUMBER) @@ -145,7 +143,5 @@
int gpio_is_native(int gpio_num) { - u16 gpio_base = get_gpio_base(); - - return !(inl(gpio_base + GPIO_CONFIG0(gpio_num)) & 1); + return !(inl(get_gpio_base() + GPIO_CONFIG0(gpio_num)) & 1); } diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h index fbad7d0..ca8f843 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.h +++ b/src/southbridge/intel/lynxpoint/lp_gpio.h @@ -152,10 +152,10 @@ /* Configure GPIOs with mainboard provided settings */ void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[]);
-/* get GPIO pin value */ +/* Get GPIO pin value */ int get_gpio(int gpio_num); /* - * get a number comprised of multiple GPIO values. gpio_num_array points to + * Get a number comprised of multiple GPIO values. gpio_num_array points to * the array of gpio pin numbers to scan, terminated by -1. */ unsigned int get_gpios(const int *gpio_num_array); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 7e1355a..02ea34c 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -63,15 +63,14 @@ static void pch_enable_serial_irqs(struct device *dev) { /* Set packet length and toggle silent mode bit for one frame. */ - pci_write_config8(dev, SERIRQ_CNTL, - (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); + pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); #if !CONFIG(SERIRQ_CONTINUOUS_MODE) - pci_write_config8(dev, SERIRQ_CNTL, - (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); + pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); #endif }
-/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control +/* + * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control * 0x00 - 0000 = Reserved * 0x01 - 0001 = Reserved * 0x02 - 0010 = Reserved @@ -108,12 +107,13 @@ pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
- /* Eric Biederman once said we should let the OS do this. + /* + * Eric Biederman once said we should let the OS do this. * I am not so sure anymore he was right. */
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin=0, int_line=0; + u8 int_pin = 0, int_line = 0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) continue; @@ -140,19 +140,17 @@ config_t *config = dev->chip_info; u32 reg32 = 0;
- /* An array would be much nicer here, or some - * other method of doing this. - */ - reg32 |= (config->gpi0_routing & 0x03) << 0; - reg32 |= (config->gpi1_routing & 0x03) << 2; - reg32 |= (config->gpi2_routing & 0x03) << 4; - reg32 |= (config->gpi3_routing & 0x03) << 6; - reg32 |= (config->gpi4_routing & 0x03) << 8; - reg32 |= (config->gpi5_routing & 0x03) << 10; - reg32 |= (config->gpi6_routing & 0x03) << 12; - reg32 |= (config->gpi7_routing & 0x03) << 14; - reg32 |= (config->gpi8_routing & 0x03) << 16; - reg32 |= (config->gpi9_routing & 0x03) << 18; + /* An array would be much nicer here, or some other method of doing this. */ + reg32 |= (config->gpi0_routing & 0x03) << 0; + reg32 |= (config->gpi1_routing & 0x03) << 2; + reg32 |= (config->gpi2_routing & 0x03) << 4; + reg32 |= (config->gpi3_routing & 0x03) << 6; + reg32 |= (config->gpi4_routing & 0x03) << 8; + reg32 |= (config->gpi5_routing & 0x03) << 10; + reg32 |= (config->gpi6_routing & 0x03) << 12; + reg32 |= (config->gpi7_routing & 0x03) << 14; + reg32 |= (config->gpi8_routing & 0x03) << 16; + reg32 |= (config->gpi9_routing & 0x03) << 18; reg32 |= (config->gpi10_routing & 0x03) << 20; reg32 |= (config->gpi11_routing & 0x03) << 22; reg32 |= (config->gpi12_routing & 0x03) << 24; @@ -175,7 +173,8 @@ int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option;
- /* Which state do we want to goto after g3 (power restored)? + /* + * Which state do we want to go to after G3 (power restored)? * 0 == S0 Full On * 1 == S5 Soft Off * @@ -218,7 +217,7 @@ reg8 &= 0x0f; /* Higher Nibble must be 0 */ reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ // reg8 &= ~(1 << 2); /* PCI SERR# Enable */ - reg8 |= (1 << 2); /* PCI SERR# Disable for now */ + reg8 |= (1 << 2); /* PCI SERR# Disable for now */ outb(reg8, 0x61);
reg8 = inb(0x70); @@ -254,14 +253,14 @@ enable_alt_smi(config->alt_gp_smi_en);
/* Set up power management block and determine sleep mode */ - reg32 = inl(pmbase + 0x04); // PM1_CNT - reg32 &= ~(7 << 10); // SLP_TYP - reg32 |= (1 << 0); // SCI_EN + reg32 = inl(pmbase + 0x04); // PM1_CNT + reg32 &= ~(7 << 10); // SLP_TYP + reg32 |= (1 << 0); // SCI_EN outl(reg32, pmbase + 0x04);
/* Clear magic status bits to prevent unexpected wake */ reg32 = RCBA32(0x3310); - reg32 |= (1 << 4)|(1 << 5)|(1 << 0); + reg32 |= (1 << 4) | (1 << 5) | (1 << 0); RCBA32(0x3310) = reg32;
reg16 = RCBA16(0x3f02); @@ -336,8 +335,7 @@
pch_config_rcba(lpt_lp_pm_rcba);
- pci_write_config32(dev, 0xac, - pci_read_config32(dev, 0xac) | (1 << 21)); + pci_write_config32(dev, 0xac, pci_read_config32(dev, 0xac) | (1 << 21));
pch_iobp_update(0xED00015C, ~(1 << 11), 0x00003700); pch_iobp_update(0xED000118, ~0UL, 0x00c00000); @@ -402,14 +400,14 @@ RCBA32_OR(0x900, (1 << 14));
reg32 = RCBA32(CG); - reg32 |= (1 << 22); // HDA Dynamic - reg32 |= (1UL << 31); // LPC Dynamic - reg32 |= (1 << 16); // PCIe Dynamic - reg32 |= (1 << 27); // HPET Dynamic - reg32 |= (1 << 28); // GPIO Dynamic + reg32 |= (1 << 22); // HDA Dynamic + reg32 |= (1UL << 31); // LPC Dynamic + reg32 |= (1 << 16); // PCIe Dynamic + reg32 |= (1 << 27); // HPET Dynamic + reg32 |= (1 << 28); // GPIO Dynamic RCBA32(CG) = reg32;
- RCBA32_OR(0x38c0, 0x7); // SPI Dynamic + RCBA32_OR(0x38c0, 0x7); // SPI Dynamic }
static void enable_lp_clock_gating(struct device *dev) @@ -447,25 +445,25 @@
reg32 = RCBA32(CG); if (RCBA32(0x3454) & (1 << 4)) - reg32 &= ~(1 << 29); // LPC Dynamic + reg32 &= ~(1 << 29); // LPC Dynamic else - reg32 |= (1 << 29); // LPC Dynamic - reg32 |= (1UL << 31); // LP LPC - reg32 |= (1 << 30); // LP BLA - reg32 |= (1 << 28); // GPIO Dynamic - reg32 |= (1 << 27); // HPET Dynamic - reg32 |= (1 << 26); // Generic Platform Event Clock + reg32 |= (1 << 29); // LPC Dynamic + reg32 |= (1UL << 31); // LP LPC + reg32 |= (1 << 30); // LP BLA + reg32 |= (1 << 28); // GPIO Dynamic + reg32 |= (1 << 27); // HPET Dynamic + reg32 |= (1 << 26); // Generic Platform Event Clock if (RCBA32(BUC) & PCH_DISABLE_GBE) - reg32 |= (1 << 23); // GbE Static - reg32 |= (1 << 22); // HDA Dynamic - reg32 |= (1 << 16); // PCI Dynamic + reg32 |= (1 << 23); // GbE Static + reg32 |= (1 << 22); // HDA Dynamic + reg32 |= (1 << 16); // PCI Dynamic RCBA32(CG) = reg32;
- RCBA32_OR(0x3434, 0x7); // LP LPC + RCBA32_OR(0x3434, 0x7); // LP LPC
- RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); // SATA + RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); // SATA
- RCBA32_OR(0x38c0, 0x3c07); // SPI Dynamic + RCBA32_OR(0x38c0, 0x3c07); // SPI Dynamic
pch_iobp_update(0xCF000000, ~0UL, 0x00007001); pch_iobp_update(0xCE00C000, ~1UL, 0x00000000); // bit0=0 in BWG 1.4.0 @@ -503,7 +501,7 @@ * Enable DMI ASPM in the PCH */ RCBA32_AND_OR(0x2304, ~(1 << 10), 0); - RCBA32_OR(0x21a4, (1 << 11)|(1 << 10)); + RCBA32_OR(0x21a4, (1 << 11) | (1 << 10)); RCBA32_OR(0x21a8, 0x3); }
@@ -617,8 +615,7 @@ * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size, - int index) +static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size, int index) { struct resource *res;
@@ -631,8 +628,7 @@ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; }
-static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, - int index) +static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, int index) { /* * Check if the register is enabled. If so and the base exceeds the @@ -657,8 +653,7 @@ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* GPIOBASE */ - pch_lpc_add_io_resource(dev, get_gpiobase(), DEFAULT_GPIOSIZE, - GPIO_BASE); + pch_lpc_add_io_resource(dev, get_gpiobase(), DEFAULT_GPIOSIZE, GPIO_BASE);
/* PMBASE */ pch_lpc_add_io_resource(dev, get_pmbase(), 256, PMBASE); @@ -882,8 +877,7 @@ }
static unsigned long southbridge_write_acpi_tables(const struct device *device, - unsigned long start, - struct acpi_rsdp *rsdp) + unsigned long start, struct acpi_rsdp *rsdp) { unsigned long current; acpi_hpet_t *hpet; @@ -967,7 +961,8 @@ 0x9c43, /* LP Premium SKU */ 0x9c45, /* LP Mainstream SKU */ 0x9c47, /* LP Value SKU */ - 0 }; + 0 +};
static const struct pci_driver pch_lpc __pci_driver = { .ops = &device_ops, diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h index 2a05233..19d06c3 100644 --- a/src/southbridge/intel/lynxpoint/me.h +++ b/src/southbridge/intel/lynxpoint/me.h @@ -103,64 +103,64 @@ #define ME_HFS2_PHASE_HOST_COMM 6 /* Current State - Based on Infra Progress values. */ /* ROM State */ -#define ME_HFS2_STATE_ROM_BEGIN 0 -#define ME_HFS2_STATE_ROM_DISABLE 6 +#define ME_HFS2_STATE_ROM_BEGIN 0 +#define ME_HFS2_STATE_ROM_DISABLE 6 /* BUP State */ -#define ME_HFS2_STATE_BUP_INIT 0 -#define ME_HFS2_STATE_BUP_DIS_HOST_WAKE 1 -#define ME_HFS2_STATE_BUP_FLOW_DET 4 -#define ME_HFS2_STATE_BUP_VSCC_ERR 8 -#define ME_HFS2_STATE_BUP_CHECK_STRAP 0xa -#define ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT 0xb -#define ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP 0xd -#define ME_HFS2_STATE_BUP_M3 0x11 -#define ME_HFS2_STATE_BUP_M0 0x12 -#define ME_HFS2_STATE_BUP_FLOW_DET_ERR 0x13 -#define ME_HFS2_STATE_BUP_M3_CLK_ERR 0x15 +#define ME_HFS2_STATE_BUP_INIT 0 +#define ME_HFS2_STATE_BUP_DIS_HOST_WAKE 1 +#define ME_HFS2_STATE_BUP_FLOW_DET 4 +#define ME_HFS2_STATE_BUP_VSCC_ERR 8 +#define ME_HFS2_STATE_BUP_CHECK_STRAP 0xa +#define ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT 0xb +#define ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP 0xd +#define ME_HFS2_STATE_BUP_M3 0x11 +#define ME_HFS2_STATE_BUP_M0 0x12 +#define ME_HFS2_STATE_BUP_FLOW_DET_ERR 0x13 +#define ME_HFS2_STATE_BUP_M3_CLK_ERR 0x15 #define ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING 0x17 -#define ME_HFS2_STATE_BUP_M3_KERN_LOAD 0x18 -#define ME_HFS2_STATE_BUP_T32_MISSING 0x1c -#define ME_HFS2_STATE_BUP_WAIT_DID 0x1f -#define ME_HFS2_STATE_BUP_WAIT_DID_FAIL 0x20 -#define ME_HFS2_STATE_BUP_DID_NO_FAIL 0x21 -#define ME_HFS2_STATE_BUP_ENABLE_UMA 0x22 -#define ME_HFS2_STATE_BUP_ENABLE_UMA_ERR 0x23 -#define ME_HFS2_STATE_BUP_SEND_DID_ACK 0x24 -#define ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR 0x25 -#define ME_HFS2_STATE_BUP_M0_CLK 0x26 -#define ME_HFS2_STATE_BUP_M0_CLK_ERR 0x27 -#define ME_HFS2_STATE_BUP_TEMP_DIS 0x28 -#define ME_HFS2_STATE_BUP_M0_KERN_LOAD 0x32 +#define ME_HFS2_STATE_BUP_M3_KERN_LOAD 0x18 +#define ME_HFS2_STATE_BUP_T32_MISSING 0x1c +#define ME_HFS2_STATE_BUP_WAIT_DID 0x1f +#define ME_HFS2_STATE_BUP_WAIT_DID_FAIL 0x20 +#define ME_HFS2_STATE_BUP_DID_NO_FAIL 0x21 +#define ME_HFS2_STATE_BUP_ENABLE_UMA 0x22 +#define ME_HFS2_STATE_BUP_ENABLE_UMA_ERR 0x23 +#define ME_HFS2_STATE_BUP_SEND_DID_ACK 0x24 +#define ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR 0x25 +#define ME_HFS2_STATE_BUP_M0_CLK 0x26 +#define ME_HFS2_STATE_BUP_M0_CLK_ERR 0x27 +#define ME_HFS2_STATE_BUP_TEMP_DIS 0x28 +#define ME_HFS2_STATE_BUP_M0_KERN_LOAD 0x32 /* Policy Module State */ -#define ME_HFS2_STATE_POLICY_ENTRY 0 -#define ME_HFS2_STATE_POLICY_RCVD_S3 3 -#define ME_HFS2_STATE_POLICY_RCVD_S4 4 -#define ME_HFS2_STATE_POLICY_RCVD_S5 5 -#define ME_HFS2_STATE_POLICY_RCVD_UPD 6 -#define ME_HFS2_STATE_POLICY_RCVD_PCR 7 -#define ME_HFS2_STATE_POLICY_RCVD_NPCR 8 -#define ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE 9 -#define ME_HFS2_STATE_POLICY_RCVD_AC_DC 0xa -#define ME_HFS2_STATE_POLICY_RCVD_DID 0xb -#define ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND 0xc -#define ME_HFS2_STATE_POLICY_VSCC_INVALID 0xd -#define ME_HFS2_STATE_POLICY_FPB_ERR 0xe -#define ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR 0xf -#define ME_HFS2_STATE_POLICY_VSCC_NO_MATCH 0x10 +#define ME_HFS2_STATE_POLICY_ENTRY 0 +#define ME_HFS2_STATE_POLICY_RCVD_S3 3 +#define ME_HFS2_STATE_POLICY_RCVD_S4 4 +#define ME_HFS2_STATE_POLICY_RCVD_S5 5 +#define ME_HFS2_STATE_POLICY_RCVD_UPD 6 +#define ME_HFS2_STATE_POLICY_RCVD_PCR 7 +#define ME_HFS2_STATE_POLICY_RCVD_NPCR 8 +#define ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE 9 +#define ME_HFS2_STATE_POLICY_RCVD_AC_DC 0xa +#define ME_HFS2_STATE_POLICY_RCVD_DID 0xb +#define ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND 0xc +#define ME_HFS2_STATE_POLICY_VSCC_INVALID 0xd +#define ME_HFS2_STATE_POLICY_FPB_ERR 0xe +#define ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR 0xf +#define ME_HFS2_STATE_POLICY_VSCC_NO_MATCH 0x10 /* Current PM Event Values */ -#define ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE 0 -#define ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR 1 -#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET 2 -#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR 3 -#define ME_HFS2_PMEVENT_CLEAN_ME_RESET 4 -#define ME_HFS2_PMEVENT_ME_RESET_EXCEPTION 5 -#define ME_HFS2_PMEVENT_PSEUDO_ME_RESET 6 -#define ME_HFS2_PMEVENT_S0MO_SXM3 7 -#define ME_HFS2_PMEVENT_SXM3_S0M0 8 -#define ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET 9 -#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3 0xa -#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb -#define ME_HFS2_PMEVENT_SXMX_SXMOFF 0xc +#define ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE 0 +#define ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR 1 +#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET 2 +#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR 3 +#define ME_HFS2_PMEVENT_CLEAN_ME_RESET 4 +#define ME_HFS2_PMEVENT_ME_RESET_EXCEPTION 5 +#define ME_HFS2_PMEVENT_PSEUDO_ME_RESET 6 +#define ME_HFS2_PMEVENT_S0MO_SXM3 7 +#define ME_HFS2_PMEVENT_SXM3_S0M0 8 +#define ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET 9 +#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3 0xa +#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb +#define ME_HFS2_PMEVENT_SXMX_SXMOFF 0xc
struct me_hfs2 { u32 bist_in_progress: 1; @@ -185,7 +185,7 @@ #define PCI_ME_HERES 0xbc #define PCI_ME_EXT_SHA1 0x00 #define PCI_ME_EXT_SHA256 0x02 -#define PCI_ME_HER(x) (0xc0+(4*(x))) +#define PCI_ME_HER(x) (0xc0 + (4 * (x)))
struct me_heres { u32 extend_reg_algorithm: 4; @@ -325,31 +325,30 @@ * structures follows the ordering in the ME9 BWG. */
-#define MBP_APPID_KERNEL 1 -#define MBP_APPID_INTEL_AT 3 -#define MBP_APPID_HWA 4 -#define MBP_APPID_ICC 5 -#define MBP_APPID_NFC 6 +#define MBP_APPID_KERNEL 1 +#define MBP_APPID_INTEL_AT 3 +#define MBP_APPID_HWA 4 +#define MBP_APPID_ICC 5 +#define MBP_APPID_NFC 6 /* Kernel items: */ -#define MBP_KERNEL_FW_VER_ITEM 1 -#define MBP_KERNEL_FW_CAP_ITEM 2 -#define MBP_KERNEL_ROM_BIST_ITEM 3 -#define MBP_KERNEL_PLAT_KEY_ITEM 4 -#define MBP_KERNEL_FW_TYPE_ITEM 5 -#define MBP_KERNEL_MFS_FAILURE_ITEM 6 -#define MBP_KERNEL_PLAT_TIME_ITEM 7 +#define MBP_KERNEL_FW_VER_ITEM 1 +#define MBP_KERNEL_FW_CAP_ITEM 2 +#define MBP_KERNEL_ROM_BIST_ITEM 3 +#define MBP_KERNEL_PLAT_KEY_ITEM 4 +#define MBP_KERNEL_FW_TYPE_ITEM 5 +#define MBP_KERNEL_MFS_FAILURE_ITEM 6 +#define MBP_KERNEL_PLAT_TIME_ITEM 7 /* Intel AT items: */ -#define MBP_INTEL_AT_STATE_ITEM 1 +#define MBP_INTEL_AT_STATE_ITEM 1 /* ICC Items: */ -#define MBP_ICC_PROFILE_ITEM 1 +#define MBP_ICC_PROFILE_ITEM 1 /* HWA Items: */ -#define MBP_HWA_REQUEST_ITEM 1 +#define MBP_HWA_REQUEST_ITEM 1 /* NFC Items: */ -#define MBP_NFC_SUPPORT_DATA_ITEM 1 +#define MBP_NFC_SUPPORT_DATA_ITEM 1
#define MBP_MAKE_IDENT(appid, item) ((appid << 8) | item) -#define MBP_IDENT(appid, item) \ - MBP_MAKE_IDENT(MBP_APPID_##appid, MBP_##appid##_##item##_ITEM) +#define MBP_IDENT(appid, item) MBP_MAKE_IDENT(MBP_APPID_##appid, MBP_##appid##_##item##_ITEM)
typedef struct { u32 mbp_size : 8; diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 8914edf..79d47da 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -86,7 +86,6 @@ /* * ME/MEI access helpers using memcpy to avoid aliasing. */ - static inline void mei_read_dword_ptr(void *ptr, int offset) { u32 dword = read32(mei_base_address + (offset/sizeof(u32))); @@ -272,8 +271,8 @@ return 0; }
-static int mei_send_header(u8 me_address, u8 host_address, - void *header, int header_len, int complete) +static int mei_send_header(u8 me_address, u8 host_address, void *header, int header_len, + int complete) { struct mei_header mei = { .client_address = me_address, @@ -284,8 +283,7 @@ return mei_send_packet(&mei, header); }
-static int mei_recv_msg(void *header, int header_bytes, - void *rsp_data, int rsp_bytes) +static int mei_recv_msg(void *header, int header_bytes, void *rsp_data, int rsp_bytes) { struct mei_header mei_rsp; struct mei_csr me, host; @@ -344,8 +342,8 @@
/* Make sure caller passed a buffer with enough space */ if (ndata != (rsp_bytes >> 2)) { - printk(BIOS_ERR, "ME: not enough room in response buffer: " - "%u != %u\n", ndata, rsp_bytes >> 2); + printk(BIOS_ERR, "ME: not enough room in response buffer: %u != %u\n", + ndata, rsp_bytes >> 2); return -1; }
@@ -384,8 +382,7 @@ return 0;
/* Read header and data */ - if (mei_recv_msg(&mkhi_rsp, sizeof(mkhi_rsp), - rsp_data, rsp_bytes) < 0) + if (mei_recv_msg(&mkhi_rsp, sizeof(mkhi_rsp), rsp_data, rsp_bytes) < 0) return -1;
if (!mkhi_rsp.is_response || @@ -422,7 +419,7 @@ }
/* - * mbp clear routine. This will wait for the ME to indicate that + * MBP clear routine. This will wait for the ME to indicate that * the MBP has been read and cleared. */ #ifdef __SIMPLE_DEVICE__ @@ -479,8 +476,7 @@ };
/* Send request and wait for response */ - if (mei_sendrecv_mkhi(&mkhi, &rule_id, sizeof(u32), - &cap_msg, sizeof(cap_msg)) < 0) { + if (mei_sendrecv_mkhi(&mkhi, &rule_id, sizeof(u32), &cap_msg, sizeof(cap_msg)) < 0) { printk(BIOS_ERR, "ME: GET FWCAPS message failed\n"); return -1; } @@ -499,20 +495,20 @@ return; }
- print_cap("Full Network manageability", cap->full_net); - print_cap("Regular Network manageability", cap->std_net); - print_cap("Manageability", cap->manageability); - print_cap("IntelR Anti-Theft (AT)", cap->intel_at); - print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls); - print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc); - print_cap("ICC Over Clocking", cap->icc_over_clocking); - print_cap("Protected Audio Video Path (PAVP)", cap->pavp); - print_cap("IPV6", cap->ipv6); - print_cap("KVM Remote Control (KVM)", cap->kvm); - print_cap("Outbreak Containment Heuristic (OCH)", cap->och); - print_cap("Virtual LAN (VLAN)", cap->vlan); - print_cap("TLS", cap->tls); - print_cap("Wireless LAN (WLAN)", cap->wlan); + print_cap("Full Network manageability", cap->full_net); + print_cap("Regular Network manageability", cap->std_net); + print_cap("Manageability", cap->manageability); + print_cap("IntelR Anti-Theft (AT)", cap->intel_at); + print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls); + print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc); + print_cap("ICC Over Clocking", cap->icc_over_clocking); + print_cap("Protected Audio Video Path (PAVP)", cap->pavp); + print_cap("IPV6", cap->ipv6); + print_cap("KVM Remote Control (KVM)", cap->kvm); + print_cap("Outbreak Containment Heuristic (OCH)", cap->och); + print_cap("Virtual LAN (VLAN)", cap->vlan); + print_cap("TLS", cap->tls); + print_cap("Wireless LAN (WLAN)", cap->wlan); }
#if CONFIG(CHROMEOS) && 0 /* DISABLED */ @@ -569,8 +565,7 @@ u32 reg32; u16 reg16;
- mei_base_address = (u32 *) - (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); + mei_base_address = (u32 *)(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
/* S3 path will have hidden this device already */ if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) @@ -917,10 +912,7 @@ u32 data[0]; };
-/* - * mbp seems to be following its own flow, let's retrieve it in a dedicated - * function. - */ +/* MBP seems to be following its own flow, let's retrieve it in a dedicated function. */ static int __unused intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) { mbp_header mbp_hdr; @@ -1033,8 +1025,8 @@ ASSIGN_FIELD_PTR(nfc_data, &mbp->data[i+1]);
default: - printk(BIOS_ERR, "ME MBP: unknown item 0x%x @ " - "dw offset 0x%x\n", mbp->data[i], i); + printk(BIOS_ERR, "ME MBP: unknown item 0x%x @ dw offset 0x%x\n", + mbp->data[i], i); break; } i += item->length; diff --git a/src/southbridge/intel/lynxpoint/me_status.c b/src/southbridge/intel/lynxpoint/me_status.c index 045d960..6ef99ed 100644 --- a/src/southbridge/intel/lynxpoint/me_status.c +++ b/src/southbridge/intel/lynxpoint/me_status.c @@ -11,7 +11,7 @@ [ME_HFS_CWS_NORMAL] = "Normal", [ME_HFS_CWS_WAIT] = "Platform Disable Wait", [ME_HFS_CWS_TRANS] = "OP State Transition", - [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In" + [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In", };
/* HFS1[8:6] Current Operation State Values */ @@ -21,7 +21,7 @@ [ME_HFS_STATE_M3] = "M3 without UMA", [ME_HFS_STATE_M0] = "M0 without UMA", [ME_HFS_STATE_BRINGUP] = "Bring up", - [ME_HFS_STATE_ERROR] = "M0 without UMA but with error" + [ME_HFS_STATE_ERROR] = "M0 without UMA but with error", };
/* HFS[19:16] Current Operation Mode Values */ @@ -30,7 +30,7 @@ [ME_HFS_MODE_DEBUG] = "Debug", [ME_HFS_MODE_DIS] = "Soft Temporary Disable", [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper", - [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message" + [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message", };
/* HFS[15:12] Error Code Values */ @@ -38,7 +38,7 @@ [ME_HFS_ERROR_NONE] = "No Error", [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure", [ME_HFS_ERROR_IMAGE] = "Image Failure", - [ME_HFS_ERROR_DEBUG] = "Debug Failure" + [ME_HFS_ERROR_DEBUG] = "Debug Failure", };
/* HFS2[31:28] ME Progress Code */ @@ -49,30 +49,30 @@ [ME_HFS2_PHASE_POLICY] = "Policy Module", [ME_HFS2_PHASE_MODULE_LOAD] = "Module Loading", [ME_HFS2_PHASE_UNKNOWN] = "Unknown", - [ME_HFS2_PHASE_HOST_COMM] = "Host Communication" + [ME_HFS2_PHASE_HOST_COMM] = "Host Communication", };
/* HFS2[27:24] Power Management Event */ static const char *me_pmevent_values[] = { - [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] = "Clean Moff->Mx wake", - [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] = "Moff->Mx wake after an error", - [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] = "Clean global reset", - [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] = "Global reset after an error", - [ME_HFS2_PMEVENT_CLEAN_ME_RESET] = "Clean Intel ME reset", - [ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] = "Intel ME reset due to exception", - [ME_HFS2_PMEVENT_PSEUDO_ME_RESET] = "Pseudo-global reset", - [ME_HFS2_PMEVENT_S0MO_SXM3] = "S0/M0->Sx/M3", - [ME_HFS2_PMEVENT_SXM3_S0M0] = "Sx/M3->S0/M0", - [ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] = "Non-power cycle reset", - [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] = "Power cycle reset through M3", - [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] = "Power cycle reset through Moff", - [ME_HFS2_PMEVENT_SXMX_SXMOFF] = "Sx/Mx->Sx/Moff" + [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] = "Clean Moff->Mx wake", + [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] = "Moff->Mx wake after an error", + [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] = "Clean global reset", + [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] = "Global reset after an error", + [ME_HFS2_PMEVENT_CLEAN_ME_RESET] = "Clean Intel ME reset", + [ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] = "Intel ME reset due to exception", + [ME_HFS2_PMEVENT_PSEUDO_ME_RESET] = "Pseudo-global reset", + [ME_HFS2_PMEVENT_S0MO_SXM3] = "S0/M0->Sx/M3", + [ME_HFS2_PMEVENT_SXM3_S0M0] = "Sx/M3->S0/M0", + [ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] = "Non-power cycle reset", + [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] = "Power cycle reset through M3", + [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] = "Power cycle reset through Moff", + [ME_HFS2_PMEVENT_SXMX_SXMOFF] = "Sx/Mx->Sx/Moff", };
/* Progress Code 0 states */ static const char *me_progress_rom_values[] = { - [ME_HFS2_STATE_ROM_BEGIN] = "BEGIN", - [ME_HFS2_STATE_ROM_DISABLE] = "DISABLE" + [ME_HFS2_STATE_ROM_BEGIN] = "BEGIN", + [ME_HFS2_STATE_ROM_DISABLE] = "DISABLE", };
/* Progress Code 1 states */ diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index e3c5bb2..9564b76 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -25,8 +25,7 @@ static int pch_revision_id = -1;
if (pch_revision_id < 0) - pch_revision_id = pci_read_config8(pch_get_lpc_device(), - PCI_REVISION_ID); + pch_revision_id = pci_read_config8(pch_get_lpc_device(), PCI_REVISION_ID); return pch_revision_id; }
@@ -45,8 +44,7 @@ static int pch_type = -1;
if (pch_type < 0) - pch_type = pci_read_config8(pch_get_lpc_device(), - PCI_DEVICE_ID + 1); + pch_type = pci_read_config8(pch_get_lpc_device(), PCI_DEVICE_ID + 1); return pch_type; }
@@ -60,8 +58,7 @@ static u16 pmbase;
if (!pmbase) - pmbase = pci_read_config16(pch_get_lpc_device(), - PMBASE) & 0xfffc; + pmbase = pci_read_config16(pch_get_lpc_device(), PMBASE) & 0xfffc; return pmbase; }
@@ -70,8 +67,7 @@ static u16 gpiobase;
if (!gpiobase) - gpiobase = pci_read_config16(pch_get_lpc_device(), - GPIOBASE) & 0xfffc; + gpiobase = pci_read_config16(pch_get_lpc_device(), GPIOBASE) & 0xfffc; return gpiobase; }
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 19f8637..6e2bd24 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -32,7 +32,7 @@ * Bus 0:Device 22:Function 2 IDE-R * Bus 0:Device 22:Function 3 KT * Bus 0:Device 20:Function 0 xHCI Controller -*/ + */
/* PCH types */ #define PCH_TYPE_LPT 0x8c @@ -166,8 +166,7 @@ #endif
void enable_usb_bar(void); -int early_pch_init(const void *gpio_map, - const struct rcba_config_instruction *rcba_config); +int early_pch_init(const void *gpio_map, const struct rcba_config_instruction *rcba_config); void pch_enable_lpc(void); void mainboard_config_superio(void);
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index e11a0b7..79b9517 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -322,8 +322,7 @@ } }
- printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n", - rpc.orig_rpfn, rpc.new_rpfn); + printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n", rpc.orig_rpfn, rpc.new_rpfn); RCBA32(RPFN) = rpc.new_rpfn; }
@@ -358,58 +357,54 @@
/* Check Root Port Configuration. */ switch (rp) { - case 2: - /* Root Port 2 is disabled for all lane configurations - * but config 00b (4x1 links). */ - if ((rpc.strpfusecfg1 >> 14) & 0x3) { - root_port_mark_disable(dev); - return; - } + case 2: + /* Root Port 2 is disabled for all lane configs except 00b (4x1 links). */ + if ((rpc.strpfusecfg1 >> 14) & 0x3) { + root_port_mark_disable(dev); + return; + } + break; + case 3: + /* Root Port 3 is disabled in config 11b (1x4 links). */ + if (((rpc.strpfusecfg1 >> 14) & 0x3) == 0x3) { + root_port_mark_disable(dev); + return; + } + break; + case 4: + /* Root Port 4 is disabled in configs 11b (1x4 links) and 10b (2x2 links). */ + if ((rpc.strpfusecfg1 >> 14) & 0x2) { + root_port_mark_disable(dev); + return; + } + break; + case 6: + if (is_lp) break; - case 3: - /* Root Port 3 is disabled in config 11b (1x4 links). */ - if (((rpc.strpfusecfg1 >> 14) & 0x3) == 0x3) { - root_port_mark_disable(dev); - return; - } + /* Root Port 6 is disabled for all lane configs except 00b (4x1 links). */ + if ((rpc.strpfusecfg2 >> 14) & 0x3) { + root_port_mark_disable(dev); + return; + } + break; + case 7: + if (is_lp) break; - case 4: - /* Root Port 4 is disabled in configs 11b (1x4 links) - * and 10b (2x2 links). */ - if ((rpc.strpfusecfg1 >> 14) & 0x2) { - root_port_mark_disable(dev); - return; - } + /* Root Port 7 is disabled in config 11b (1x4 links). */ + if (((rpc.strpfusecfg2 >> 14) & 0x3) == 0x3) { + root_port_mark_disable(dev); + return; + } + break; + case 8: + if (is_lp) break; - case 6: - if (is_lp) - break; - /* Root Port 6 is disabled for all lane configurations - * but config 00b (4x1 links). */ - if ((rpc.strpfusecfg2 >> 14) & 0x3) { - root_port_mark_disable(dev); - return; - } - break; - case 7: - if (is_lp) - break; - /* Root Port 7 is disabled in config 11b (1x4 links). */ - if (((rpc.strpfusecfg2 >> 14) & 0x3) == 0x3) { - root_port_mark_disable(dev); - return; - } - break; - case 8: - if (is_lp) - break; - /* Root Port 8 is disabled in configs 11b (1x4 links) - * and 10b (2x2 links). */ - if ((rpc.strpfusecfg2 >> 14) & 0x2) { - root_port_mark_disable(dev); - return; - } - break; + /* Root Port 8 is disabled in configs 11b (1x4 links) and 10b (2x2 links). */ + if ((rpc.strpfusecfg2 >> 14) & 0x2) { + root_port_mark_disable(dev); + return; + } + break; }
/* Check Pin Ownership. */ diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index 8c4a8c1..f40b921 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -95,10 +95,10 @@ static u16 print_pm1_status(u16 pm1_sts) { const char *pm1_sts_bits[] = { - [0] = "TMROF", - [4] = "BM", - [5] = "GBL", - [8] = "PWRBTN", + [0] = "TMROF", + [4] = "BM", + [5] = "GBL", + [8] = "PWRBTN", [10] = "RTC", [11] = "PRBTNOR", [14] = "PCIEXPWAK", @@ -127,7 +127,6 @@ outw(events, get_pmbase() + PM1_EN); }
- /* * SMI */ @@ -135,7 +134,7 @@ /* Clear and return SMI status register */ static u32 reset_smi_status(void) { - u32 smi_sts = inl(get_pmbase() + SMI_STS); + const u32 smi_sts = inl(get_pmbase() + SMI_STS); outl(smi_sts, get_pmbase() + SMI_STS); return smi_sts; } @@ -144,13 +143,13 @@ static u32 print_smi_status(u32 smi_sts) { const char *smi_sts_bits[] = { - [2] = "BIOS", - [3] = "LEGACY_USB", - [4] = "SLP_SMI", - [5] = "APM", - [6] = "SWSMI_TMR", - [8] = "PM1", - [9] = "GPE0", + [2] = "BIOS", + [3] = "LEGACY_USB", + [4] = "SLP_SMI", + [5] = "APM", + [6] = "SWSMI_TMR", + [8] = "PM1", + [9] = "GPE0", [10] = "GPI", [11] = "MCSMI", [12] = "DEVMON", @@ -198,7 +197,6 @@ outl(smi_en, get_pmbase() + SMI_EN); }
- /* * ALT_GP_SMI */ @@ -298,7 +296,6 @@ } }
- /* * TCO */ @@ -324,13 +321,13 @@ static u32 print_tco_status(u32 tco_sts) { const char *tco_sts_bits[] = { - [0] = "NMI2SMI", - [1] = "SW_TCO", - [2] = "TCO_INT", - [3] = "TIMEOUT", - [7] = "NEWCENTURY", - [8] = "BIOSWR", - [9] = "DMISCI", + [0] = "NMI2SMI", + [1] = "SW_TCO", + [2] = "TCO_INT", + [3] = "TIMEOUT", + [7] = "NEWCENTURY", + [8] = "BIOSWR", + [9] = "DMISCI", [10] = "DMISMI", [12] = "DMISERR", [13] = "SLVSEL", @@ -368,7 +365,6 @@ enable_gpe(TCOSCI_EN); }
- /* * GPE0 */ @@ -377,7 +373,7 @@ static u32 reset_gpe_status(u16 sts_reg, u16 en_reg) { u32 gpe0_sts = inl(get_pmbase() + sts_reg); - u32 gpe0_en = inl(get_pmbase() + en_reg); + u32 gpe0_en = inl(get_pmbase() + en_reg);
outl(gpe0_sts, get_pmbase() + sts_reg);
@@ -415,12 +411,12 @@ static u32 clear_lpt_gpe_status(void) { const char *gpe0_sts_bits_low[] = { - [1] = "HOTPLUG", - [2] = "SWGPE", - [6] = "TCO_SCI", - [7] = "SMB_WAK", - [8] = "RI", - [9] = "PCI_EXP", + [1] = "HOTPLUG", + [2] = "SWGPE", + [6] = "TCO_SCI", + [7] = "SMB_WAK", + [8] = "RI", + [9] = "PCI_EXP", [10] = "BATLOW", [11] = "PME", [13] = "PME_B0", @@ -442,8 +438,8 @@ [31] = "GPIO15", }; const char *gpe0_sts_bits_high[] = { - [3] = "GPIO27", - [6] = "WADT", + [3] = "GPIO27", + [6] = "WADT", [24] = "GPIO17", [25] = "GPIO19", [26] = "GPIO21", @@ -455,23 +451,21 @@ };
/* High bits */ - print_gpe_status(reset_gpe_status(GPE0_STS_2, GPE0_EN_2), - gpe0_sts_bits_high); + print_gpe_status(reset_gpe_status(GPE0_STS_2, GPE0_EN_2), gpe0_sts_bits_high);
/* Standard GPE and GPIO 0-31 */ - return print_gpe_status(reset_gpe_status(GPE0_STS, GPE0_EN), - gpe0_sts_bits_low); + return print_gpe_status(reset_gpe_status(GPE0_STS, GPE0_EN), gpe0_sts_bits_low); }
/* Print, clear, and return LynxPoint-LP GPE0 status */ static u32 clear_lpt_lp_gpe_status(void) { const char *gpe0_sts_4_bits[] = { - [1] = "HOTPLUG", - [2] = "SWGPE", - [6] = "TCO_SCI", - [7] = "SMB_WAK", - [9] = "PCI_EXP", + [1] = "HOTPLUG", + [2] = "SWGPE", + [6] = "TCO_SCI", + [7] = "SMB_WAK", + [9] = "PCI_EXP", [10] = "BATLOW", [11] = "PME", [12] = "ME", @@ -490,8 +484,7 @@ print_gpe_gpio(reset_gpe_status(LP_GPE0_STS_3, LP_GPE0_EN_3), 64);
/* Standard GPE */ - return print_gpe_status(reset_gpe_status(LP_GPE0_STS_4, LP_GPE0_EN_4), - gpe0_sts_4_bits); + return print_gpe_status(reset_gpe_status(LP_GPE0_STS_4, LP_GPE0_EN_4), gpe0_sts_4_bits); }
/* Clear all GPE status and return "standard" GPE event status */ @@ -528,7 +521,7 @@ /* Enable a standard GPE */ void enable_gpe(u32 mask) { - u32 gpe0_reg = pch_is_lp() ? LP_GPE0_EN_4 : GPE0_EN; + const u32 gpe0_reg = pch_is_lp() ? LP_GPE0_EN_4 : GPE0_EN; u32 gpe0_en = inl(get_pmbase() + gpe0_reg); gpe0_en |= mask; outl(gpe0_en, get_pmbase() + gpe0_reg); @@ -537,7 +530,7 @@ /* Disable a standard GPE */ void disable_gpe(u32 mask) { - u32 gpe0_reg = pch_is_lp() ? LP_GPE0_EN_4 : GPE0_EN; + const u32 gpe0_reg = pch_is_lp() ? LP_GPE0_EN_4 : GPE0_EN; u32 gpe0_en = inl(get_pmbase() + gpe0_reg); gpe0_en &= ~mask; outl(gpe0_en, get_pmbase() + gpe0_reg); diff --git a/src/southbridge/intel/lynxpoint/rcba.c b/src/southbridge/intel/lynxpoint/rcba.c index 9f62cd3..de5a90b 100644 --- a/src/southbridge/intel/lynxpoint/rcba.c +++ b/src/southbridge/intel/lynxpoint/rcba.c @@ -11,8 +11,7 @@ u32 value;
rc = rcba_config; - while (rc->command != RCBA_COMMAND_END) - { + while (rc->command != RCBA_COMMAND_END) { if ((rc->command & RCBA_REG_SIZE_MASK) == RCBA_REG_SIZE_16) { switch (rc->command & RCBA_COMMAND_MASK) { case RCBA_COMMAND_SET: diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index ab96d62..9515473 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -311,7 +311,7 @@ }
static struct pci_operations sata_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, };
static struct device_operations sata_ops = { diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index e093508..accc51b 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -154,46 +154,39 @@ case PCI_DEVFN(21, 0): /* SDMA */ sio_index = SIO_ID_SDMA; serialio_init_once(config->sio_acpi_mode); - serialio_d21_mode(sio_index, SIO_PIN_INTB, - config->sio_acpi_mode); + serialio_d21_mode(sio_index, SIO_PIN_INTB, config->sio_acpi_mode); break; case PCI_DEVFN(21, 1): /* I2C0 */ sio_index = SIO_ID_I2C0; serialio_d21_ltr(bar0); serialio_i2c_voltage_sel(bar0, config->sio_i2c0_voltage); - serialio_d21_mode(sio_index, SIO_PIN_INTC, - config->sio_acpi_mode); + serialio_d21_mode(sio_index, SIO_PIN_INTC, config->sio_acpi_mode); break; case PCI_DEVFN(21, 2): /* I2C1 */ sio_index = SIO_ID_I2C1; serialio_d21_ltr(bar0); serialio_i2c_voltage_sel(bar0, config->sio_i2c1_voltage); - serialio_d21_mode(sio_index, SIO_PIN_INTC, - config->sio_acpi_mode); + serialio_d21_mode(sio_index, SIO_PIN_INTC, config->sio_acpi_mode); break; case PCI_DEVFN(21, 3): /* SPI0 */ sio_index = SIO_ID_SPI0; serialio_d21_ltr(bar0); - serialio_d21_mode(sio_index, SIO_PIN_INTC, - config->sio_acpi_mode); + serialio_d21_mode(sio_index, SIO_PIN_INTC, config->sio_acpi_mode); break; case PCI_DEVFN(21, 4): /* SPI1 */ sio_index = SIO_ID_SPI1; serialio_d21_ltr(bar0); - serialio_d21_mode(sio_index, SIO_PIN_INTC, - config->sio_acpi_mode); + serialio_d21_mode(sio_index, SIO_PIN_INTC, config->sio_acpi_mode); break; case PCI_DEVFN(21, 5): /* UART0 */ sio_index = SIO_ID_UART0; serialio_d21_ltr(bar0); - serialio_d21_mode(sio_index, SIO_PIN_INTD, - config->sio_acpi_mode); + serialio_d21_mode(sio_index, SIO_PIN_INTD, config->sio_acpi_mode); break; case PCI_DEVFN(21, 6): /* UART1 */ sio_index = SIO_ID_UART1; serialio_d21_ltr(bar0); - serialio_d21_mode(sio_index, SIO_PIN_INTD, - config->sio_acpi_mode); + serialio_d21_mode(sio_index, SIO_PIN_INTD, config->sio_acpi_mode); break; case PCI_DEVFN(23, 0): /* SDIO */ sio_index = SIO_ID_SDIO; @@ -221,7 +214,7 @@ }
static struct pci_operations pci_ops = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, };
static struct device_operations device_ops = { diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c index e78d85d..48d4349 100644 --- a/src/southbridge/intel/lynxpoint/smbus.c +++ b/src/southbridge/intel/lynxpoint/smbus.c @@ -51,12 +51,12 @@ }
static struct smbus_bus_operations lops_smbus_bus = { - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, + .read_byte = lsmbus_read_byte, + .write_byte = lsmbus_write_byte, };
static struct pci_operations smbus_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, };
static void smbus_read_resources(struct device *dev) diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 9d57554..5fedc5e 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -43,7 +43,8 @@ enable_pm1(PWRBTN_EN | GBL_EN); disable_gpe(PME_B0_EN);
- /* Enable SMI generation: + /* + * Enable SMI generation: * - on APMC writes (io 0xb2) * - on writes to SLP_EN (sleep states) * - on writes to GBL_RLS (bios commands) diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 8bbe3fe..5d58cac 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -350,11 +350,9 @@ { u16 pm1_sts = clear_pm1_status();
- /* While OSPM is not active, poweroff immediately - * on a power button event. - */ + /* While OSPM is not active, poweroff immediately on a power button event */ if (pm1_sts & PWRBTN_STS) { - // power button pressed + /* Power button pressed */ elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON); disable_pm1_control(-1UL); enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10)); @@ -387,8 +385,6 @@ printk(BIOS_DEBUG, "Microcontroller SMI.\n"); }
- - static void southbridge_smi_tco(void) { u32 tco_sts = clear_tco_status(); @@ -403,19 +399,18 @@ bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
if (bios_cntl & 1) { - /* BWE is RW, so the SMI was caused by a + /* + * BWE is RW, so the SMI was caused by a * write to BWE, not by a write to the BIOS */
- /* This is the place where we notice someone - * is trying to tinker with the BIOS. We are - * trying to be nice and just ignore it. A more - * resolute answer would be to power down the - * box. + /* This is the place where we notice someone is + * trying to tinker with the BIOS. We are trying + * to be nice and just ignore it. A more resolute + * answer would be to power down the box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, - (bios_cntl & ~1)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ @@ -439,6 +434,7 @@ static void southbridge_smi_monitor(void) { #define IOTRAP(x) (trap_sts & (1 << x)) + u32 trap_sts, trap_cycle; u32 data, mask = 0; int i; @@ -447,7 +443,7 @@ RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR
trap_cycle = RCBA32(0x1e10); - for (i=16; i<20; i++) { + for (i = 16; i < 20; i++) { if (trap_cycle & (1 << i)) mask |= (0xff << ((i - 16) << 2)); } @@ -460,8 +456,8 @@ return; }
- /* IOTRAP(2) currently unused - * IOTRAP(1) currently unused */ + /* IOTRAP(2) currently unused */ + /* IOTRAP(1) currently unused */
/* IOTRAP(0) SMIC */ if (IOTRAP(0)) { @@ -476,14 +472,15 @@ // Fall through to debug }
- printk(BIOS_DEBUG, " trapped io address = 0x%x\n", - trap_cycle & 0xfffc); - for (i=0; i < 4; i++) - if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); + + for (i = 0; i < 4; i++) { + if (IOTRAP(i)) + printk(BIOS_DEBUG, " TRAP = %d\n", i); + } printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); - printk(BIOS_DEBUG, " read/write: %s\n", - (trap_cycle & (1 << 24)) ? "read" : "write"); + printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
if (!(trap_cycle & (1 << 24))) { /* Write Cycle */ @@ -538,7 +535,8 @@ int i; u32 smi_sts;
- /* We need to clear the SMI status registers, or we won't see what's + /* + * We need to clear the SMI status registers, or we won't see what's * happening in the following calls. */ smi_sts = clear_smi_status(); @@ -550,8 +548,7 @@ southbridge_smi[i](); } else { printk(BIOS_DEBUG, - "SMI_STS[%d] occurred, but no " - "handler available.\n", i); + "SMI_STS[%d] occurred, but no handler available.\n", i); } } } diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index 52b3ed8..74ef021 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -127,7 +127,7 @@ pch_iobp_update(0xe5004001, ~0, (1 << 7)|(1 << 6));
/* Dx:F0:DCh[5,2,1] = 111b - * Dx:F0:DCh[0] = 1b when EHCI controller is disabled */ + Dx:F0:DCh[0] = 1b when EHCI controller is disabled */ reg32 = pci_read_config32(dev, 0xdc); reg32 |= (1 << 5) | (1 << 2) | (1 << 1); pci_write_config32(dev, 0xdc, reg32); @@ -150,8 +150,7 @@ printk(BIOS_DEBUG, "done.\n"); }
-static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) +static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device) { u8 access_cntl;
diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 49a6cfc..5ab5a2c 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -258,7 +258,7 @@ reg32 |= (1 << 21) | (1 << 20); } else { /* D20:F0:40h[21,20,18,17,8] = 11111b */ - reg32 |= (1 << 21)|(1 << 20)|(1 << 18)|(1 << 17)|(1 << 8); + reg32 |= (1 << 21) | (1 << 20) | (1 << 18) | (1 << 17) | (1 << 8); }
/* Avoid writing upper byte as it is write-once */