Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52105 )
Change subject: soc/intel: Drop unreferenced `SkipExtGfxScan` ......................................................................
soc/intel: Drop unreferenced `SkipExtGfxScan`
This option is not referenced anywhere. Drop it.
Change-Id: I296d20b4a13b73260aa5343ea72bdd3c770b7656 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/alderlake/chip.h M src/soc/intel/cannonlake/chip.h M src/soc/intel/elkhartlake/chip.h M src/soc/intel/icelake/chip.h M src/soc/intel/jasperlake/chip.h M src/soc/intel/tigerlake/chip.h 6 files changed, 0 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/52105/1
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 164d1b9..92d53a9 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -149,7 +149,6 @@ IGD_SM_56MB = 0xFD, IGD_SM_60MB = 0xFE, } IgdDvmt50PreAlloc; - uint8_t SkipExtGfxScan;
/* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index a9b6c4c..5bdbdee 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -196,9 +196,6 @@ /* Heci related */ uint8_t DisableHeciRetry;
- /* Gfx related */ - uint8_t SkipExtGfxScan; - uint8_t Device4Enable;
/* CPU PL2/4 Config diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index c3a7ac1..a148cf1 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -128,9 +128,6 @@ /* Enable if SD Card Power Enable Signal is Active High */ uint8_t SdCardPowerEnableActiveHigh;
- /* Gfx related */ - uint8_t SkipExtGfxScan; - uint8_t Device4Enable;
/* HeciEnabled decides the state of Heci1 at end of boot diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index bef9adb..4db8a4d 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -129,9 +129,6 @@ /* Heci related */ uint8_t Heci3Enabled;
- /* Gfx related */ - uint8_t SkipExtGfxScan; - uint8_t Device4Enable;
/* HeciEnabled decides the state of Heci1 at end of boot diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index c25ccbf..a1cdeeec 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -130,9 +130,6 @@ uint16_t ImonSlope; uint16_t ImonOffset;
- /* Gfx related */ - uint8_t SkipExtGfxScan; - /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index af9b310..16260a1 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -264,9 +264,6 @@ /* SMBus */ uint8_t SmbusEnable;
- /* Gfx related */ - uint8_t SkipExtGfxScan; - uint8_t Device4Enable;
/* HeciEnabled decides the state of Heci1 at end of boot