Attention is currently required from: Jeremy Soller.
Hello Jeremy Soller,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/87131?usp=email
to review the following change.
Change subject: soc/intel: Add Arrow Lake-H IDs ......................................................................
soc/intel: Add Arrow Lake-H IDs
Change-Id: I8430914edd02954cbb38592bff896733b01c735d Ref: Intel Arrow Lake-H/U EDS, Volume 1 (#777369, rev 2.0) Signed-off-by: Jeremy Soller jeremy@system76.com Signed-off-by: Tim Crawford tcrawford@system76.com --- M src/drivers/intel/ish/ish.c M src/include/cpu/intel/cpu_ids.h M src/include/device/pci_ids.h M src/soc/intel/common/block/cnvi/cnvi.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/hda/hda.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/tracehub/tracehub.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/meteorlake/bootblock/report_platform.c M src/soc/intel/meteorlake/chip.h 26 files changed, 95 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/87131/1
diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c index 5dd4a79..c5beac2 100644 --- a/src/drivers/intel/ish/ish.c +++ b/src/drivers/intel/ish/ish.c @@ -89,6 +89,7 @@ PCI_DID_INTEL_PTL_U_H_ISHB, PCI_DID_INTEL_LNL_ISHB, PCI_DID_INTEL_MTL_ISHB, + PCI_DID_INTEL_ARL_ISHB, PCI_DID_INTEL_CNL_ISHB, PCI_DID_INTEL_CML_ISHB, PCI_DID_INTEL_TGL_ISHB, diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index 9ef74b9..a084172 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -84,6 +84,7 @@ #define CPUID_RAPTORLAKE_Q0 0xb06a3 #define CPUID_LUNARLAKE_A0_1 0xb06d0 #define CPUID_LUNARLAKE_A0_2 0xb06d1 +#define CPUID_ARROWLAKE_H_A0 0xc0652 #define CPUID_PANTHERLAKE_A0 0xc06c0 #define CPUID_SNOWRIDGE_A0 0x80660 #define CPUID_SNOWRIDGE_A1 0x80661 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 7d695b2..e827882 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2182,6 +2182,7 @@ #define PCI_DID_INTEL_TGL_ISHB 0xa0fc #define PCI_DID_INTEL_TGL_H_ISHB 0x43fc #define PCI_DID_INTEL_MTL_ISHB 0x7e45 +#define PCI_DID_INTEL_ARL_ISHB 0x7745 #define PCI_DID_INTEL_ADL_N_ISHB 0x54fc #define PCI_DID_INTEL_ADL_P_ISHB 0x51fc #define PCI_DID_INTEL_LNL_ISHB 0xa845 @@ -3141,6 +3142,7 @@ #define PCI_DID_INTEL_MTL_ESPI_5 0x7e05 #define PCI_DID_INTEL_MTL_ESPI_6 0x7e06 #define PCI_DID_INTEL_MTL_ESPI_7 0x7e07 +#define PCI_DID_INTEL_ARL_H_ESPI 0x7702 #define PCI_DID_INTEL_RPP_P_ESPI_0 0x5180 #define PCI_DID_INTEL_RPP_P_ADP_P_ESPI_1 0x5181 #define PCI_DID_INTEL_RPP_P_ADP_P_ESPI_2 0x5182 @@ -3604,6 +3606,16 @@ #define PCI_DID_INTEL_MTL_IOE_P_PCIE_RP11 0x7ecb #define PCI_DID_INTEL_MTL_IOE_P_PCIE_RP12 0x7ecc
+#define PCI_DID_INTEL_ARL_SOC_PCIE_RP1 0x7738 +#define PCI_DID_INTEL_ARL_SOC_PCIE_RP2 0x7739 +#define PCI_DID_INTEL_ARL_SOC_PCIE_RP3 0x773a +#define PCI_DID_INTEL_ARL_SOC_PCIE_RP4 0x773b +#define PCI_DID_INTEL_ARL_SOC_PCIE_RP5 0x773c +#define PCI_DID_INTEL_ARL_SOC_PCIE_RP6 0x773d +#define PCI_DID_INTEL_ARL_SOC_PCIE_RP7 0x773e +#define PCI_DID_INTEL_ARL_SOC_PCIE_RP8 0x773f +#define PCI_DID_INTEL_ARL_SOC_PCIE_RP9 0x774d + #define PCI_DID_INTEL_RPL_P_PCIE_RP1 0xa74d #define PCI_DID_INTEL_RPL_P_PCIE_RP2 0xa70d #define PCI_DID_INTEL_RPL_P_PCIE_RP3 0xa72d @@ -3764,6 +3776,7 @@ #define PCI_DID_INTEL_ADP_M_SATA_2 0x54d7 #define PCI_DID_INTEL_ADP_M_SATA_3 0x282a #define PCI_DID_INTEL_MTL_SATA 0x7e63 +#define PCI_DID_INTEL_ARL_SATA 0x7763 #define PCI_DID_INTEL_RPP_P_SATA_1 0x51d3 #define PCI_DID_INTEL_RPP_P_SATA_2 0x51d7 #define PCI_DID_INTEL_RPP_S_SATA 0x7a62 @@ -3793,6 +3806,7 @@ #define PCI_DID_INTEL_MTL_SOC_PMC 0x7e21 #define PCI_DID_INTEL_MTL_IOE_M_PMC 0x7ebe #define PCI_DID_INTEL_MTL_IOE_P_PMC 0x7ece +#define PCI_DID_INTEL_ARL_SOC_PMC 0x7721 #define PCI_DID_INTEL_RPP_P_PMC 0x51a1 #define PCI_DID_INTEL_RPP_S_PMC 0x7a21 #define PCI_DID_INTEL_LNL_PMC 0xa821 @@ -3922,6 +3936,13 @@ #define PCI_DID_INTEL_MTL_I2C4 0x7e50 #define PCI_DID_INTEL_MTL_I2C5 0x7e51
+#define PCI_DID_INTEL_ARL_I2C0 0x7778 +#define PCI_DID_INTEL_ARL_I2C1 0x7779 +#define PCI_DID_INTEL_ARL_I2C2 0x777A +#define PCI_DID_INTEL_ARL_I2C3 0x777B +#define PCI_DID_INTEL_ARL_I2C4 0x7750 +#define PCI_DID_INTEL_ARL_I2C5 0x7751 + #define PCI_DID_INTEL_LNL_I2C0 0xa878 #define PCI_DID_INTEL_LNL_I2C1 0xa879 #define PCI_DID_INTEL_LNL_I2C2 0xa87a @@ -4021,6 +4042,10 @@ #define PCI_DID_INTEL_MTL_UART1 0x7e26 #define PCI_DID_INTEL_MTL_UART2 0x7e52
+#define PCI_DID_INTEL_ARL_UART0 0x7725 +#define PCI_DID_INTEL_ARL_UART1 0x7726 +#define PCI_DID_INTEL_ARL_UART2 0x7752 + #define PCI_DID_INTEL_LNL_UART0 0xa825 #define PCI_DID_INTEL_LNL_UART1 0xa826 #define PCI_DID_INTEL_LNL_UART2 0xa852 @@ -4126,6 +4151,11 @@ #define PCI_DID_INTEL_MTL_GSPI1 0x7e30 #define PCI_DID_INTEL_MTL_GSPI2 0x7e46
+#define PCI_DID_INTEL_ARL_HWSEQ_SPI 0x7723 +#define PCI_DID_INTEL_ARL_GSPI0 0x7727 +#define PCI_DID_INTEL_ARL_GSPI1 0x7730 +#define PCI_DID_INTEL_ARL_GSPI2 0x7746 + #define PCI_DID_INTEL_LNL_HWSEQ_SPI 0xa823 #define PCI_DID_INTEL_LNL_GSPI0 0xa827 #define PCI_DID_INTEL_LNL_GSPI1 0xa830 @@ -4284,6 +4314,7 @@ #define PCI_DID_INTEL_MTL_P_GT2_3 0x7d55 #define PCI_DID_INTEL_MTL_P_GT2_4 0x7d60 #define PCI_DID_INTEL_MTL_P_GT2_5 0x7dd5 +#define PCI_DID_INTEL_ARL_H_GT2 0x7d51 #define PCI_DID_INTEL_RPL_HX_GT1 0xa788 #define PCI_DID_INTEL_RPL_HX_GT2 0xa78b #define PCI_DID_INTEL_RPL_HX_GT3 0x4688 @@ -4433,6 +4464,8 @@ #define PCI_DID_INTEL_MTL_P_ID_3 0x7d14 #define PCI_DID_INTEL_MTL_P_ID_4 0x7d15 #define PCI_DID_INTEL_MTL_P_ID_5 0x7d16 +#define PCI_DID_INTEL_ARL_H_ID_1 0x7d06 +#define PCI_DID_INTEL_ARL_H_ID_2 0x7d20 #define PCI_DID_INTEL_RPL_HX_ID_1 0xa702 #define PCI_DID_INTEL_RPL_HX_ID_2 0xa729 #define PCI_DID_INTEL_RPL_HX_ID_3 0xa728 @@ -4488,6 +4521,7 @@ #define PCI_DID_INTEL_ADP_S_SMBUS 0x7aa3 #define PCI_DID_INTEL_ADP_M_N_SMBUS 0x54a3 #define PCI_DID_INTEL_MTL_SMBUS 0x7e22 +#define PCI_DID_INTEL_ARL_SMBUS 0x7722 #define PCI_DID_INTEL_RPP_P_SMBUS 0x51a3 #define PCI_DID_INTEL_RPP_S_SMBUS 0x7a23 #define PCI_DID_INTEL_LNL_SMBUS 0xa822 @@ -4531,6 +4565,7 @@ #define PCI_DID_INTEL_MTL_XHCI 0x7e7d #define PCI_DID_INTEL_MTL_M_TCSS_XHCI 0x7eb0 #define PCI_DID_INTEL_MTL_P_TCSS_XHCI 0x7ec0 +#define PCI_DID_INTEL_ARL_XHCI 0x777d #define PCI_DID_INTEL_RPP_P_TCSS_XHCI 0xa71e #define PCI_DID_INTEL_RPP_S_XHCI 0x7a60 #define PCI_DID_INTEL_LNL_XHCI 0xa87d @@ -4564,6 +4599,7 @@ #define PCI_DID_INTEL_MTL_SOC_P2SB 0x7e20 #define PCI_DID_INTEL_MTL_IOE_M_P2SB 0x7eb8 #define PCI_DID_INTEL_MTL_IOE_P_P2SB 0x7ec8 +#define PCI_DID_INTEL_ARL_SOC_P2SB 0x7720 #define PCI_DID_INTEL_RPP_P_P2SB 0x51a0 #define PCI_DID_INTEL_RPP_S_P2SB 0x7a20 #define PCI_DID_INTEL_LNL_P2SB 0xa820 @@ -4587,6 +4623,7 @@ #define PCI_DID_INTEL_MTL_SOC_SRAM 0x7e7f #define PCI_DID_INTEL_MTL_IOE_M_SRAM 0x7ebf #define PCI_DID_INTEL_MTL_IOE_P_SRAM 0x7ecf +#define PCI_DID_INTEL_ARL_SOC_SRAM 0x777f #define PCI_DID_INTEL_LNL_SRAM 0xa87f #define PCI_DID_INTEL_PTL_H_SRAM 0xe47f #define PCI_DID_INTEL_PTL_U_H_SRAM 0xe37f @@ -4647,6 +4684,8 @@ #define PCI_DID_INTEL_MTL_AUDIO_7 0x7e2e #define PCI_DID_INTEL_MTL_AUDIO_8 0x7e2f
+#define PCI_DID_INTEL_ARL_AUDIO 0x7728 + #define PCI_DID_INTEL_LNL_AUDIO_1 0xa828 #define PCI_DID_INTEL_LNL_AUDIO_2 0xa829 #define PCI_DID_INTEL_LNL_AUDIO_3 0xa82a @@ -4717,6 +4756,7 @@ #define PCI_DID_INTEL_RPP_S_CSE2 0x7a6c #define PCI_DID_INTEL_RPP_S_CSE3 0x7a6d #define PCI_DID_INTEL_MTL_CSE0 0x7e70 +#define PCI_DID_INTEL_ARL_CSE0 0x7770 #define PCI_DID_INTEL_LNL_CSE0 0xa870 #define PCI_DID_INTEL_PTL_H_CSE0 0xe470 #define PCI_DID_INTEL_PTL_U_H_CSE0 0xe370 @@ -4744,6 +4784,7 @@ #define PCI_DID_INTEL_MTL_XDCI 0x7e7e #define PCI_DID_INTEL_MTL_M_TCSS_XDCI 0x7eb1 #define PCI_DID_INTEL_MTL_P_TCSS_XDCI 0x7ec1 +#define PCI_DID_INTEL_ARL_XDCI 0x777e #define PCI_DID_INTEL_PTL_H_XDCI 0xe47e #define PCI_DID_INTEL_PTL_U_H_XDCI 0xe37e
@@ -4899,6 +4940,7 @@ #define PCI_DID_INTEL_MTL_CNVI_WIFI_1 0x7e41 #define PCI_DID_INTEL_MTL_CNVI_WIFI_2 0x7e42 #define PCI_DID_INTEL_MTL_CNVI_WIFI_3 0x7e43 +#define PCI_DID_INTEL_ARL_CNVI_WIFI 0x7740 #define PCI_DID_INTEL_RPL_S_CNVI_WIFI_0 0x7a70 #define PCI_DID_INTEL_RPL_S_CNVI_WIFI_1 0x7a71 #define PCI_DID_INTEL_RPL_S_CNVI_WIFI_2 0x7a72 @@ -4941,6 +4983,7 @@
/* Intel Trace Hub */ #define PCI_DID_INTEL_MTL_TRACEHUB 0x7e24 +#define PCI_DID_INTEL_ARL_TRACEHUB 0x7724 #define PCI_DID_INTEL_RPL_TRACEHUB 0xa76f #define PCI_DID_INTEL_PTL_H_TRACEHUB 0xe424 #define PCI_DID_INTEL_PTL_U_H_TRACEHUB 0xe324 @@ -4963,6 +5006,10 @@ #define PCI_DID_INTEL_PTL_H_THC0_SPI 0xe449 #define PCI_DID_INTEL_PTL_H_THC1_I2C 0xe44a #define PCI_DID_INTEL_PTL_H_THC1_SPI 0xe44b +#define PCI_DID_INTEL_ARL_THC0_1 0x7748 +#define PCI_DID_INTEL_ARL_THC0_2 0x7749 +#define PCI_DID_INTEL_ARL_THC1_1 0x774a +#define PCI_DID_INTEL_ARL_THC1_2 0x774b
#define PCI_VID_COMPUTONE 0x8e0e #define PCI_DID_COMPUTONE_IP2EX 0x0291 diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c index 1c668ba..d939738 100644 --- a/src/soc/intel/common/block/cnvi/cnvi.c +++ b/src/soc/intel/common/block/cnvi/cnvi.c @@ -457,6 +457,7 @@ PCI_DID_INTEL_MTL_CNVI_WIFI_1, PCI_DID_INTEL_MTL_CNVI_WIFI_2, PCI_DID_INTEL_MTL_CNVI_WIFI_3, + PCI_DID_INTEL_ARL_CNVI_WIFI, PCI_DID_INTEL_CML_LP_CNVI_WIFI, PCI_DID_INTEL_CML_H_CNVI_WIFI, PCI_DID_INTEL_CNL_LP_CNVI_WIFI, diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 95e52d5..3fd5232 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -39,6 +39,7 @@ { X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_2, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_METEORLAKE_B0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_METEORLAKE_C0, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_ARROWLAKE_H_A0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_SKYLAKE_C0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_SKYLAKE_D0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_SKYLAKE_HQ0, CPUID_EXACT_MATCH_MASK }, diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 2e0f2db..c38af0b 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1513,6 +1513,7 @@ PCI_DID_INTEL_PTL_U_H_CSE0, PCI_DID_INTEL_LNL_CSE0, PCI_DID_INTEL_MTL_CSE0, + PCI_DID_INTEL_ARL_CSE0, PCI_DID_INTEL_APL_CSE0, PCI_DID_INTEL_GLK_CSE0, PCI_DID_INTEL_CNL_CSE0, diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index ab0e116..59593bc 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -45,6 +45,7 @@ PCI_DID_INTEL_MTL_AUDIO_6, PCI_DID_INTEL_MTL_AUDIO_7, PCI_DID_INTEL_MTL_AUDIO_8, + PCI_DID_INTEL_ARL_AUDIO, PCI_DID_INTEL_RPP_P_AUDIO, PCI_DID_INTEL_RPP_S_AUDIO_1, PCI_DID_INTEL_RPP_S_AUDIO_2, diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 4551961..b6f0724 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -568,6 +568,7 @@ PCI_DID_INTEL_LWB_SPI_SUPER, PCI_DID_INTEL_MCC_SPI0, PCI_DID_INTEL_MTL_HWSEQ_SPI, + PCI_DID_INTEL_ARL_HWSEQ_SPI, PCI_DID_INTEL_RPP_S_HWSEQ_SPI, PCI_DID_INTEL_SPR_HWSEQ_SPI, PCI_DID_INTEL_TGP_SPI0, diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index cf3e7b1..25d389c 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -363,6 +363,7 @@ PCI_DID_INTEL_MTL_P_GT2_3, PCI_DID_INTEL_MTL_P_GT2_4, PCI_DID_INTEL_MTL_P_GT2_5, + PCI_DID_INTEL_ARL_H_GT2, PCI_DID_INTEL_APL_IGD_HD_505, PCI_DID_INTEL_APL_IGD_HD_500, PCI_DID_INTEL_CNL_GT2_ULX_1, diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index 59ecb50..7af1b25 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -53,6 +53,7 @@ PCI_DID_INTEL_MTL_AUDIO_6, PCI_DID_INTEL_MTL_AUDIO_7, PCI_DID_INTEL_MTL_AUDIO_8, + PCI_DID_INTEL_ARL_AUDIO, PCI_DID_INTEL_RPP_P_AUDIO, PCI_DID_INTEL_RPP_S_AUDIO_1, PCI_DID_INTEL_RPP_S_AUDIO_2, diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index 3c2f211..a4e6aae 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -198,6 +198,12 @@ PCI_DID_INTEL_MTL_I2C3, PCI_DID_INTEL_MTL_I2C4, PCI_DID_INTEL_MTL_I2C5, + PCI_DID_INTEL_ARL_I2C0, + PCI_DID_INTEL_ARL_I2C1, + PCI_DID_INTEL_ARL_I2C2, + PCI_DID_INTEL_ARL_I2C3, + PCI_DID_INTEL_ARL_I2C4, + PCI_DID_INTEL_ARL_I2C5, PCI_DID_INTEL_APL_I2C0, PCI_DID_INTEL_APL_I2C1, PCI_DID_INTEL_APL_I2C2, diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index db06db9..2b6e665 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -231,6 +231,7 @@ PCI_DID_INTEL_MTL_ESPI_5, PCI_DID_INTEL_MTL_ESPI_6, PCI_DID_INTEL_MTL_ESPI_7, + PCI_DID_INTEL_ARL_H_ESPI, PCI_DID_INTEL_RPP_P_ESPI_0, PCI_DID_INTEL_RPP_P_ADP_P_ESPI_1, PCI_DID_INTEL_RPP_P_ADP_P_ESPI_2, diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 27e969c..2bc3c70 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -141,6 +141,7 @@ PCI_DID_INTEL_PTL_U_H_P2SB, PCI_DID_INTEL_LNL_P2SB, PCI_DID_INTEL_MTL_SOC_P2SB, + PCI_DID_INTEL_ARL_SOC_P2SB, PCI_DID_INTEL_RPP_P_P2SB, PCI_DID_INTEL_APL_P2SB, PCI_DID_INTEL_GLK_P2SB, diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index ddea3b6..677d257 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -112,6 +112,15 @@ PCI_DID_INTEL_MTL_IOE_P_PCIE_RP10, PCI_DID_INTEL_MTL_IOE_P_PCIE_RP11, PCI_DID_INTEL_MTL_IOE_P_PCIE_RP12, + PCI_DID_INTEL_ARL_SOC_PCIE_RP1, + PCI_DID_INTEL_ARL_SOC_PCIE_RP2, + PCI_DID_INTEL_ARL_SOC_PCIE_RP3, + PCI_DID_INTEL_ARL_SOC_PCIE_RP4, + PCI_DID_INTEL_ARL_SOC_PCIE_RP5, + PCI_DID_INTEL_ARL_SOC_PCIE_RP6, + PCI_DID_INTEL_ARL_SOC_PCIE_RP7, + PCI_DID_INTEL_ARL_SOC_PCIE_RP8, + PCI_DID_INTEL_ARL_SOC_PCIE_RP9, PCI_DID_INTEL_LWB_PCIE_RP1, PCI_DID_INTEL_LWB_PCIE_RP2, PCI_DID_INTEL_LWB_PCIE_RP3, diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index ca1c4b0..57b00c1 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -117,6 +117,7 @@ PCI_DID_INTEL_MTL_SOC_PMC, PCI_DID_INTEL_MTL_IOE_M_PMC, PCI_DID_INTEL_MTL_IOE_P_PMC, + PCI_DID_INTEL_ARL_SOC_PMC, PCI_DID_INTEL_RPP_P_PMC, PCI_DID_INTEL_DNV_PMC, PCI_DID_INTEL_LWB_PMC, diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index ca61c68..ae51efa 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -36,6 +36,7 @@
static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_SATA, + PCI_DID_INTEL_ARL_SATA, PCI_DID_INTEL_RPP_P_SATA_1, PCI_DID_INTEL_RPP_P_SATA_2, PCI_DID_INTEL_RPP_S_SATA, diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index 37e0cd2..62a44b4 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -53,6 +53,7 @@ PCI_DID_INTEL_PTL_U_H_SMBUS, PCI_DID_INTEL_LNL_SMBUS, PCI_DID_INTEL_MTL_SMBUS, + PCI_DID_INTEL_ARL_SMBUS, PCI_DID_INTEL_RPP_P_SMBUS, PCI_DID_INTEL_RPP_S_SMBUS, PCI_DID_INTEL_APL_SMBUS, diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 74f9e31..beac292 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -137,6 +137,9 @@ PCI_DID_INTEL_MTL_GSPI0, PCI_DID_INTEL_MTL_GSPI1, PCI_DID_INTEL_MTL_GSPI2, + PCI_DID_INTEL_ARL_GSPI0, + PCI_DID_INTEL_ARL_GSPI1, + PCI_DID_INTEL_ARL_GSPI2, PCI_DID_INTEL_APL_SPI0, PCI_DID_INTEL_APL_SPI1, PCI_DID_INTEL_APL_SPI2, diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index da7022d..62cfab5 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -41,6 +41,7 @@ PCI_DID_INTEL_MTL_IOE_M_SRAM, PCI_DID_INTEL_MTL_IOE_P_SRAM, PCI_DID_INTEL_MTL_CRASHLOG_SRAM, + PCI_DID_INTEL_ARL_SOC_SRAM, PCI_DID_INTEL_APL_SRAM, PCI_DID_INTEL_GLK_SRAM, PCI_DID_INTEL_CMP_SRAM, diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 098c3c4..f91dd98 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -438,6 +438,8 @@ PCI_DID_INTEL_MTL_P_ID_3, PCI_DID_INTEL_MTL_P_ID_4, PCI_DID_INTEL_MTL_P_ID_5, + PCI_DID_INTEL_ARL_H_ID_1, + PCI_DID_INTEL_ARL_H_ID_2, PCI_DID_INTEL_GLK_NB, PCI_DID_INTEL_APL_NB, PCI_DID_INTEL_CNL_ID_U, diff --git a/src/soc/intel/common/block/tracehub/tracehub.c b/src/soc/intel/common/block/tracehub/tracehub.c index ba56c4c..c9f4228 100644 --- a/src/soc/intel/common/block/tracehub/tracehub.c +++ b/src/soc/intel/common/block/tracehub/tracehub.c @@ -45,6 +45,7 @@ PCI_DID_INTEL_PTL_H_TRACEHUB, PCI_DID_INTEL_PTL_U_H_TRACEHUB, PCI_DID_INTEL_MTL_TRACEHUB, + PCI_DID_INTEL_ARL_TRACEHUB, PCI_DID_INTEL_RPL_TRACEHUB, 0 }; diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index ef83f53..e42db42 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -369,6 +369,9 @@ PCI_DID_INTEL_MTL_UART0, PCI_DID_INTEL_MTL_UART1, PCI_DID_INTEL_MTL_UART2, + PCI_DID_INTEL_ARL_UART0, + PCI_DID_INTEL_ARL_UART1, + PCI_DID_INTEL_ARL_UART2, PCI_DID_INTEL_APL_UART0, PCI_DID_INTEL_APL_UART1, PCI_DID_INTEL_APL_UART2, diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index 86625da..bd3917c 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -31,6 +31,7 @@ PCI_DID_INTEL_PTL_H_XDCI, PCI_DID_INTEL_PTL_U_H_XDCI, PCI_DID_INTEL_MTL_XDCI, + PCI_DID_INTEL_ARL_XDCI, PCI_DID_INTEL_APL_XDCI, PCI_DID_INTEL_CNL_LP_XDCI, PCI_DID_INTEL_GLK_XDCI, diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 6d35f39..1cdf21f 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -135,6 +135,7 @@ PCI_DID_INTEL_PTL_U_H_XHCI, PCI_DID_INTEL_LNL_XHCI, PCI_DID_INTEL_MTL_XHCI, + PCI_DID_INTEL_ARL_XHCI, PCI_DID_INTEL_APL_XHCI, PCI_DID_INTEL_CNL_LP_XHCI, PCI_DID_INTEL_GLK_XHCI, diff --git a/src/soc/intel/meteorlake/bootblock/report_platform.c b/src/soc/intel/meteorlake/bootblock/report_platform.c index 4056989..6e0ed96 100644 --- a/src/soc/intel/meteorlake/bootblock/report_platform.c +++ b/src/soc/intel/meteorlake/bootblock/report_platform.c @@ -22,6 +22,7 @@ { CPUID_METEORLAKE_A0_2, "MeteorLake A0" }, { CPUID_METEORLAKE_B0, "MeteorLake B0" }, { CPUID_METEORLAKE_C0, "MeteorLake C0" }, + { CPUID_ARROWLAKE_H_A0, "ArrowLake-H A0" }, };
static struct { @@ -34,6 +35,8 @@ { PCI_DID_INTEL_MTL_P_ID_3, "MeteorLake P" }, { PCI_DID_INTEL_MTL_P_ID_4, "MeteorLake P" }, { PCI_DID_INTEL_MTL_P_ID_5, "MeteorLake P" }, + { PCI_DID_INTEL_ARL_H_ID_1, "ArrowLake-H" }, + { PCI_DID_INTEL_ARL_H_ID_2, "ArrowLake-H" }, };
static struct { @@ -48,6 +51,7 @@ { PCI_DID_INTEL_MTL_ESPI_5, "MeteorLake SOC" }, { PCI_DID_INTEL_MTL_ESPI_6, "MeteorLake SOC" }, { PCI_DID_INTEL_MTL_ESPI_7, "MeteorLake SOC" }, + { PCI_DID_INTEL_ARL_H_ESPI, "ArrowLake-H SOC" }, };
static struct { @@ -60,6 +64,7 @@ { PCI_DID_INTEL_MTL_P_GT2_3, "MeteorLake-P GT2" }, { PCI_DID_INTEL_MTL_P_GT2_4, "Meteorlake-P GT2" }, { PCI_DID_INTEL_MTL_P_GT2_5, "Meteorlake-P GT2" }, + { PCI_DID_INTEL_ARL_H_GT2, "ArrowLake-H GT2" }, };
static inline uint8_t get_dev_revision(pci_devfn_t dev) diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index fa65773..4ef8fd5 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -65,6 +65,8 @@ { PCI_DID_INTEL_MTL_P_ID_2, MTL_P_282_242_CORE, TDP_15W }, { PCI_DID_INTEL_MTL_P_ID_3, MTL_P_682_482_CORE, TDP_28W }, { PCI_DID_INTEL_MTL_P_ID_1, MTL_P_682_482_CORE, TDP_28W }, + { PCI_DID_INTEL_ARL_H_ID_1, MTL_P_682_482_CORE, TDP_28W }, + { PCI_DID_INTEL_ARL_H_ID_2, MTL_P_682_482_CORE, TDP_28W }, };
/* Types of display ports */