[coreboot-gerrit] Change in coreboot[master]: mb/google/brya: Disable PCH USB2 phy power gating for felwinter

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63294 )

Change subject: mb/google/brya: Disable PCH USB2 phy power gating for felwinter
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mb/google/brya: Disable PCH USB2 phy power gating for felwinter

The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for felwinter board. Please refer Intel doc#723158 for
more information.

BUG=b:221461379, b:226020977
TEST=Verify the build for felwinter board

Signed-off-by: Sridhar Siricilla 
Change-Id: I25033ea218fa3154eb99af6be43c4198f4db3bcb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63294
Tested-by: build bot (Jenkins) 
Reviewed-by: Subrata Banik 
---
M src/mainboard/google/brya/variants/felwinter/overridetree.cb
1 file changed, 4 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
index a89ad95..d2ecf4a 100644
--- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb
+++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
@@ -44,6 +44,10 @@
    	[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
    }"

+	# As per Intel Advisory doc#723158, the change is required to prevent possible
+	# display flickering issue.
+	register "usb2_phy_sus_pg_disable" = "1"
+
    # Intel Common SoC Config
    #+-------------------+---------------------------+
    #| Field             |  Value                    |