Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32136 )
Change subject: mb/google/hatch: Change the DEVSLP reset config to PLTRST ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/#/c/32136/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32136/2//COMMIT_MSG@10 PS2, Line 10: However on hatch the SATA power is still enabled.
Why? Hardware design, driver issue?
The expectation is that the PCH leaves the DEVSLP signal in high Z state so that it can be pulled high. But since the pad_rst_config is being preserved across deep sleep the signal is not in high Z. This can be fixed in 2 ways,
1. Add a load switch to power the SATA device and turn it off when going to sleep. 2. Make the pin to be in High Z state when PLTRST is asserted(which is this change).
Hatch is primarily designed for S0ix in mind (in which DEVSLP is well managed) and not S3. So it is not really an issue but a design choice.
https://review.coreboot.org/#/c/32136/2//COMMIT_MSG@11 PS2, Line 11: And
And fits on the previous line.
Done