[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Set FSP UPD to unlock GPP_A12 to use as FPMCU_RST

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32110 )

Change subject: soc/intel/cannonlake: Set FSP UPD to unlock GPP_A12 to use as FPMCU_RST
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Patch Set 3:

(3 comments)

https://review.coreboot.org/#/c/32110/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/#/c/32110/3//COMMIT_MSG@7 
PS3, Line 7: GPP_A12
Isn't this all GPIOs?

https://review.coreboot.org/#/c/32110/3//COMMIT_MSG@7 
PS3, Line 7: FPMCU_RST
This doesn't apply to all CNL boards.

https://review.coreboot.org/#/c/32110/3//COMMIT_MSG@9 
PS3, Line 9: GPP_A12 is being GPIO padlocked and cannot used in kernel. Unlock the
           : GPIO pads to export this pin in kernel to be used as FPMCU_RST.
This is specific to hatch.