Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35595 )
Change subject: soc/intel/cannonlake: Fix FSP UPDs settings with disabled GBE ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35595/2/src/soc/intel/cannonlake/fs... File src/soc/intel/cannonlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/35595/2/src/soc/intel/cannonlake/fs... PS2, Line 196: SlpS0WithGbeSupport
This line should not be required, right?
Hi Fuquan, I think the default of this UPD is 1 (enable)
# !BSF NAME:{SlpS0WithGbeSupport} TYPE:{Combo} OPTION:{$EN_DIS} # !BSF HELP:{Enable/Disable SLP_S0 with GBE Support. Default is 0 for PCH-LP, WHL V0 Stepping CPU and 1 for PCH-H Series. 0: Disable, 1: Enable} gPlatformFspPkgTokenSpaceGuid.SlpS0WithGbeSupport | * | 0x01 | 0x01
https://review.coreboot.org/c/coreboot/+/35595/2/src/soc/intel/cannonlake/fs... PS2, Line 207: && params->PchLanEnable
So, as per discussion it looks like: […]
ok, i will add comment here. thanks.