[coreboot-gerrit] Change in coreboot[master]: soc/intel/{cnl, icl}: Cache the TSEG region

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35026 )

Change subject: soc/intel/{cnl, icl}: Cache the TSEG region
......................................................................

soc/intel/{cnl, icl}: Cache the TSEG region

Change-Id: Ie92d2c9e50fa299db1cd8c57a6047ea3adaf1452
Signed-off-by: Subrata Banik 
---
M src/soc/intel/cannonlake/romstage/romstage.c
M src/soc/intel/icelake/romstage/romstage.c
2 files changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/35026/1

diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 9f02c8b..9e2f2f8 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -165,5 +165,8 @@
    /* Cache the ROM as WP just below 4GiB. */
    postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);

+	/* Cache the TSEG region. */
+	enable_tseg_cache(&pcf);
+
    run_postcar_phase(&pcf);
 }
diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c
index 8312f17..4d0cc17 100644
--- a/src/soc/intel/icelake/romstage/romstage.c
+++ b/src/soc/intel/icelake/romstage/romstage.c
@@ -149,5 +149,8 @@
    /* Cache the ROM as WP just below 4GiB. */
    postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);

+	/* Cache the TSEG region. */
+	enable_tseg_cache(&pcf);
+
    run_postcar_phase(&pcf);
 }