Aaron Durbin (adurbin@chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14549
-gerrit
commit a1e7b970d303b90bc770bb7183551a84c454e8d6 Author: Aaron Durbin adurbin@chromium.org Date: Fri Apr 29 12:43:27 2016 -0500
drivers/intel/fsp1_1: fix linking romstage when SEPARATE_VERSTAGE used
The skylake-based Chromebooks use a separate verstage which runs just after bootblock and prior to romstage. However, that config is not enabled for coreboot.org so when C_ENVIRONMENT_BOOTBLOCK changes were done it wasn't observed that the Chromebook config failed because 2 _start symbols were present. Remedy this failure by using the common car_stage_entry symbol for taking over control flow.
Change-Id: I3f29b90ba8e3786b2106a34e49e6d1f9831dcc7c Signed-off-by: Aaron Durbin adurbin@chromium.org --- src/drivers/intel/fsp1_1/romstage_after_verstage.S | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-)
diff --git a/src/drivers/intel/fsp1_1/romstage_after_verstage.S b/src/drivers/intel/fsp1_1/romstage_after_verstage.S index 739db29..2a3372f 100644 --- a/src/drivers/intel/fsp1_1/romstage_after_verstage.S +++ b/src/drivers/intel/fsp1_1/romstage_after_verstage.S @@ -16,18 +16,8 @@ #define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */
.text -.global _start -_start: - /* This is the romstage entry point when CONFIG_SEPARATE_VERSTAGE - * is used. The stack, descriptors, and gdt are already initialized - * by verstage. However, in order to maintain the semantics of - * CAR_GLOBAL variables we need to clear those to zero. */ - cld - xor %eax, %eax - movl $(_car_global_end), %ecx - movl $(_car_global_start), %edi - sub %edi, %ecx - rep stosl +.global car_stage_entry +car_stage_entry: call romstage_after_verstage #include "after_raminit.S"