[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Prevent SMI storm when setting SPI WPD bit

[Angel Pons (Code Review)]

Attention is currently required from: Nico Huber, Patrick Rudolph, Benjamin Doron, Tim Wawrzynczak.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50754 )

Change subject: soc/intel/common: Prevent SMI storm when setting SPI WPD bit
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Patch Set 1:

(1 comment)

File src/soc/intel/common/block/smm/smihandler.c:

https://review.coreboot.org/c/coreboot/+/50754/comment/536f5aae_bea548b9 
PS1, Line 363: 	if (fast_spi_wpd_status()) {
> Sorry, this discussion doesn't seem to make any sense. The logic should be: […]

Random note: Looks like the SMI# trigger for the SPI PCI device is indeed the SYNC_SS bit. So, for each of {LPC,SPI,eSPI}, we always need to clear the corresponding status bits, but only clear WPD if coreboot is configured to enforce write-protection.