Denis Carikli (GNUtoo@no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3276
-gerrit
commit aec5cb26be258f4b25250ec9e97e02381c28c4e7 Author: Denis 'GNUtoo' Carikli GNUtoo@no-log.org Date: Thu May 30 21:47:50 2013 +0200
Lenovo ThinkPad X60: Reserve memory resource in RAM for graphics.
With this commit we can see (corrupted) graphics in grub2 as a payload.
Note that using the ram directly for the framebuffer(instead of the BAR 2) is wrong, but it's the only way to prevent the tables(coreboot, ACPI etc...) from beeing overwritten when writing to the framebuffer completely.
We reserved 4M to be large (The framebuffer is 3M). and also modified setgtt accordinly.
setgtt of 768(3M) doesn't cover all the screen even if 1024x768x32bit is 3M.
Change-Id: Ie04c80d57e85f29f0134cddd462c2a5085710563 Signed-off-by: Denis 'GNUtoo' Carikli GNUtoo@no-log.org --- src/mainboard/lenovo/x60/i915.c | 2 +- src/northbridge/intel/i945/gma.c | 9 ++++++--- src/northbridge/intel/i945/northbridge.c | 12 ++++++++++++ 3 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index ef26645..7274f65 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -373,7 +373,7 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, return 0; }
- setgtt(0, 800 , physbase, 4096); + setgtt(0, 1024 , physbase, 4096);
temp = READ32(PGETLB_CTL); printk(BIOS_INFO, "GTT PGETLB_CTL register: 0x%lx\n", temp); diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index e63178d..9806ece 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -53,15 +53,18 @@ static void gma_func0_init(struct device *dev) /* This should probably run before post VBIOS init. */ printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); u32 iobase, mmiobase, physbase, graphics_base; + extern uint64_t graphics_ram_resource_base; +// extern uint64_t graphics_ram_resource_size; + iobase = dev->resource_list[1].base; mmiobase = dev->resource_list[0].base; - physbase = pci_read_config32(dev, 0x5c) & ~0xf; - graphics_base = dev->resource_list[2].base + 0x20000 ; + physbase = graphics_ram_resource_base; + graphics_base = graphics_ram_resource_base + 0x20000 ; + //dev->resource_list[2].base + 0x20000 ;
int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx); i915lightup(physbase, iobase, mmiobase, graphics_base); #endif - }
/* This doesn't reclaim stolen UMA memory, but IGD could still diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 9d97f0c..fd4b02a 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -31,6 +31,11 @@ #include <arch/acpi.h> #include "i945.h"
+#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + uint64_t graphics_ram_resource_base = 0; + uint64_t graphics_ram_resource_size = 0; +#endif + static int get_pcie_bar(u32 *base, u32 *len) { device_t dev; @@ -173,6 +178,13 @@ static void pci_domain_set_resources(device_t dev) /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk_stolen * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; +#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + graphics_ram_resource_base = ( high_tables_base - (4 * 1024 * 1024) ); + graphics_ram_resource_size = (4 * 1024 * 1024); + + reserved_ram_resource(dev, 8, graphics_ram_resource_base >> 10, + graphics_ram_resource_size >> 10); +#endif }
/* TODO We could determine how many PCIe busses we need in