[coreboot-gerrit] Change in coreboot[master]: northbridge/intel/haswell: Fix undefined behavior

[Ryan Salsamendi (Code Review)]

Ryan Salsamendi has uploaded this change for review. ( https://review.coreboot.org/20465

Change subject: northbridge/intel/haswell: Fix undefined behavior
......................................................................

northbridge/intel/haswell: Fix undefined behavior

Fix undefined behavior found by clang's -Wshift-sign-overflow, find,
and source inspection. Left shifting an int where the right operand is
> = the width of the type is undefined. Add UL suffix since it's safe

for unsigned types.

Change-Id: Id1ed2252ce3ed052730dd10b24c453c34c2ab4ff
Signed-off-by: Ryan Salsamendi 
---
M src/northbridge/intel/haswell/acpi.c
M src/northbridge/intel/haswell/early_init.c
M src/northbridge/intel/haswell/finalize.c
3 files changed, 11 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/20465/1

diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c
index 8afef00..e032948 100644
--- a/src/northbridge/intel/haswell/acpi.c
+++ b/src/northbridge/intel/haswell/acpi.c
@@ -29,6 +29,7 @@
    u32 pciexbar = 0;
    u32 pciexbar_reg;
    int max_buses;
+	u32 mask;

dev = dev_find_slot(0, PCI_DEVFN(0, 0));
    if (!dev)
@@ -40,17 +41,20 @@
    if (!(pciexbar_reg & (1 << 0)))
    	return current;

+	mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28);
    switch ((pciexbar_reg >> 1) & 3) {
    case 0: // 256MB
-		pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
+		pciexbar = pciexbar_reg & mask;
    	max_buses = 256;
    	break;
    case 1: // 128M
-		pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
+		mask |= (1 << 27);
+		pciexbar = pciexbar_reg & mask;
    	max_buses = 128;
    	break;
    case 2: // 64M
-		pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
+		mask |= (1 << 27) | (1 << 26);
+		pciexbar = pciexbar_reg & mask;
    	max_buses = 64;
    	break;
    default: // RSVD
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index f426339..a2b0f7f 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -81,7 +81,7 @@

/* GPU RC6 workaround for sighting 366252 */
    reg32 = MCHBAR32(0x5d14);
-	reg32 |= (1 << 31);
+	reg32 |= (1UL << 31);
    MCHBAR32(0x5d14) = reg32;

/* VLW */
diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c
index 5a82449..04f7356 100644
--- a/src/northbridge/intel/haswell/finalize.c
+++ b/src/northbridge/intel/haswell/finalize.c
@@ -35,11 +35,11 @@
    pci_or_config32(PCI_DEV_HSW, 0xbc, 1 << 0);	/* TOLUD */

MCHBAR32_OR(0x5500, 1 << 0);	/* PAVP */
-	MCHBAR32_OR(0x5f00, 1 << 31);	/* SA PM */
+	MCHBAR32_OR(0x5f00, 1UL << 31);	/* SA PM */
    MCHBAR32_OR(0x6020, 1 << 0);	/* UMA GFX */
    MCHBAR32_OR(0x63fc, 1 << 0);	/* VTDTRK */
-	MCHBAR32_OR(0x6800, 1 << 31);
-	MCHBAR32_OR(0x7000, 1 << 31);
+	MCHBAR32_OR(0x6800, 1UL << 31);
+	MCHBAR32_OR(0x7000, 1UL << 31);
    MCHBAR32_OR(0x77fc, 1 << 0);

/* Memory Controller Lockdown */