Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34988 )
Change subject: mediatek/mt8183: Implement the dramc init setting ......................................................................
Patch Set 22:
(4 comments)
https://review.coreboot.org/c/coreboot/+/34988/20/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/34988/20/src/soc/mediatek/mt8183/dr... PS20, Line 121: 0x0
no need to put 0 - it's automatically initialized to 0 in this case.
Done
https://review.coreboot.org/c/coreboot/+/34988/20/src/soc/mediatek/mt8183/dr... PS20, Line 122: 0x
no need to add 0
Done
https://review.coreboot.org/c/coreboot/+/34988/20/src/soc/mediatek/mt8183/dr... PS20, Line 123: 0x0
no need to add 0
Done
https://review.coreboot.org/c/coreboot/+/34988/20/src/soc/mediatek/mt8183/em... File src/soc/mediatek/mt8183/emi.c:
https://review.coreboot.org/c/coreboot/+/34988/20/src/soc/mediatek/mt8183/em... PS20, Line 22: #define LP4X_HIGH_FREQ LP4X_DDR3200
since we'll make this dynamic in future, I see no reason to keep it here as a separate define. […]
Done