27 Oct
2020
27 Oct
'20
10:32 p.m.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46852 )
Change subject: soc/intel/tigerlake: Enable TCSS XHCI device and define port aliases ......................................................................
Patch Set 1: Code-Review+2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I724ca874d3a3f6a2b43a700b0b10f77f25c53ee0
Gerrit-Change-Number: 46852
Gerrit-PatchSet: 1
Gerrit-Owner: Duncan Laurie dlaurie@chromium.org
Gerrit-Reviewer: Furquan Shaikh furquan@google.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-Comment-Date: Tue, 27 Oct 2020 21:32:35 +0000
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