Hello build bot (Jenkins), Patrick Georgi, Angel Pena Galvão, Matt DeVillier, Jeremy Soller, Paul Menzel, Subrata Banik, Youness Alaoui, Aamir Bohra, Patrick Rudolph, Piotr Król, Nico Huber, Michał Żygowski, Swift Geek (Sebastian Grzywna),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40877
to look at the new patch set (#3).
Change subject: soc/intel/skl: always enable SataPwrOptEnable ......................................................................
soc/intel/skl: always enable SataPwrOptEnable
For unknown reasons FSP skips a whole bunch of SIR (SATA Initialization Registers) when SataPwrOptEnable=0, which currently is the default. This leads to all sorts of problems and errors, for example: - links get lost - only 1.5 or 3 Gbps instead of 6 Gbps - "Unaligned Write" errors in Linux - ...
At least on two boards (supermicro/x11-lga1151-series/x11ssm-f and purism/librem13v2) SATA is not working correctly and showing such symptoms.
To let FSP correctly initialize the SATA controller, enable the option SataPwrOptEnable staticly. There is no valid reason to provide an option for breaking coreboot, anyway.
Surprisingly cml and cnl are not affected, even though they share mostly the same reference code in this regard. Thus, only skl gets changed.
Change-Id: I8531ba9743453a3118b389565517eb769b5e7929 Signed-off-by: Michael Niewöhner foss@mniewoehner.de --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 5 files changed, 6 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/40877/3