[coreboot-gerrit] Change in coreboot[master]: debug: print SR1 status

[Rizwan Qureshi (Code Review)]

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48628 )

Change subject: debug: print SR1 status
......................................................................

debug: print SR1 status

Signed-off-by: Rizwan Qureshi 
Change-Id: I2ba5d0030a3ae648e41ee23463949b998ac0b922
---
M src/console/init.c
M src/soc/intel/jasperlake/chip.c
2 files changed, 13 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48628/1

diff --git a/src/console/init.c b/src/console/init.c
index c598077..8e3f2ad 100644
--- a/src/console/init.c
+++ b/src/console/init.c
@@ -7,6 +7,7 @@
 #include <device/pci.h>
 #include <option.h>
 #include <version.h>
+#include <spi_flash.h>

#define FIRST_CONSOLE (ENV_BOOTBLOCK || (CONFIG(NO_BOOTBLOCK_CONSOLE) && ENV_ROMSTAGE))

@@ -47,6 +48,7 @@

asmlinkage void console_init(void)
 {
+	u8 spi_sts;
    init_log_level();

if (CONFIG(DEBUG_CONSOLE_INIT))
@@ -62,4 +64,7 @@
    printk(BIOS_NOTICE, "\n\ncoreboot-%s%s %s " ENV_STRING " starting (log level: %i)...\n",
           coreboot_version, coreboot_extra_version, coreboot_build,
           get_log_level());
+
+	spi_flash_status(boot_device_spi_flash(), &spi_sts);
+	printk(BIOS_DEBUG, "SPI_STATUS: 0x%x\n", spi_sts);
 }
diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c
index d34ef55..d1f11b8 100644
--- a/src/soc/intel/jasperlake/chip.c
+++ b/src/soc/intel/jasperlake/chip.c
@@ -15,6 +15,9 @@
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 #include <soc/soc_chip.h>
+#include <spi_flash.h>
+#include <console/console.h>
+

static const struct pcie_rp_group pch_rp_groups[] = {
    { .slot = PCH_DEV_SLOT_PCIE,    .count = 8 },
@@ -126,9 +129,14 @@
     * default policy that doesn't honor boards' requirements. */
    itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);

+	u8 spi_sts;
+	spi_flash_status(boot_device_spi_flash(), &spi_sts);
+	printk(BIOS_DEBUG, "SPI_STATUS before siInit: 0x%x\n", spi_sts);
    /* Perform silicon specific init. */
    fsp_silicon_init(romstage_handoff_is_resume());

+	spi_flash_status(boot_device_spi_flash(), &spi_sts);
+	printk(BIOS_DEBUG, "SPI_STATUS after siInit: 0x%x\n", spi_sts);
     /* Display FIRMWARE_VERSION_INFO_HOB */
    fsp_display_fvi_version_hob();