[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Configure GPIOs again after FSP-S is done

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31250 )

Change subject: soc/intel/cannonlake: Configure GPIOs again after FSP-S is done
......................................................................

soc/intel/cannonlake: Configure GPIOs again after FSP-S is done

FSP-S is currently configuring GPIOs that it should not. This results
in issues where mainboard devices don't behave as expected e.g. host
unable to receive TPM interrupts as the pad for the interrupt is
re-configured as something else.

Until FSP-S is fixed, this change adds a workaround by reconfiguring
GPIOs after FSP-S is run.

All mainboards need to call cnl_configure_pads instead of
gpio_configure_pads so that SoC code can maintain a reference to the
GPIO table and use that to re-configure GPIOs after FSP-S is run.

BUG=b:123721147
BRANCH=None
TEST=Verified that there are no TPM IRQ timeouts in boot log on hatch.

Change-Id: I7787aa8f185f633627bcedc7f23504bf4a5250b4
Signed-off-by: Furquan Shaikh 
Reviewed-on: https://review.coreboot.org/c/31250
Tested-by: build bot (Jenkins) 
Reviewed-by: Duncan Laurie 
---
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/cannonlake/include/soc/gpio.h
2 files changed, 35 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Duncan Laurie: Looks good to me, approved

diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 4604d80..a643954 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -140,6 +140,33 @@
 }
 #endif

+/*
+ * TODO(furquan): Get rid of this workaround once FSP is fixed. Currently, FSP-S
+ * configures GPIOs when it should not and this results in coreboot GPIO
+ * configuration being overwritten. Until FSP is fixed, maintain the reference
+ * of GPIO config table from mainboard and use that to re-configure GPIOs after
+ * FSP-S is done.
+ */
+void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads)
+{
+	static const struct pad_config *g_cfg;
+	static size_t g_num_pads;
+
+	/*
+	 * If cfg and num_pads are passed in from mainboard, maintain a
+	 * reference to the GPIO table.
+	 */
+	if ((cfg == NULL) || (num_pads == 0)) {
+		cfg = g_cfg;
+		num_pads = g_num_pads;
+	} else {
+		g_cfg = cfg;
+		g_num_pads = num_pads;
+	}
+
+	gpio_configure_pads(cfg, num_pads);
+}
+
 void soc_init_pre_device(void *chip_info)
 {
    /* Snapshot the current GPIO IRQ polarities. FSP is setting a
@@ -154,6 +181,9 @@

/* Restore GPIO IRQ polarities back to previous settings. */
    itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
+
+	/* TODO(furquan): Get rid of this workaround once FSP is fixed. */
+	cnl_configure_pads(NULL, 0);
 }

static void pci_domain_set_resources(struct device *dev)
diff --git a/src/soc/intel/cannonlake/include/soc/gpio.h b/src/soc/intel/cannonlake/include/soc/gpio.h
index cbc230a..718372d 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio.h
@@ -16,7 +16,6 @@
 #ifndef _SOC_CANNONLAKE_GPIO_H_
 #define _SOC_CANNONLAKE_GPIO_H_

-
 #if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H)
 #include <soc/gpio_defs_cnp_h.h>
 #define CROS_GPIO_DEVICE_NAME	"INT3450:00"
@@ -26,4 +25,9 @@
 #endif
 #include <intelblocks/gpio.h>

+#ifndef __ACPI__
+struct pad_config;
+void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads);
+#endif
+
 #endif