[coreboot-gerrit] Change in ...coreboot[master]: mb/google/sarien: Add delay for EC sync

[EricR Lai (Code Review)]

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32763

Change subject: mb/google/sarien: Add delay for EC sync
......................................................................

mb/google/sarien: Add delay for EC sync

Kernel will fail at async when go into s0ix.
Add a delay to let EC has some time for sync.

BUG=b:130644677
TEST= check event log only log s0ix once

Signed-off-by: Eric Lai 
Change-Id: I7ba48068f44ab2558199277f8dbbbbe9bcf249ff
---
M src/soc/intel/cannonlake/acpi/lpit.asl
1 file changed, 2 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/32763/1

diff --git a/src/soc/intel/cannonlake/acpi/lpit.asl b/src/soc/intel/cannonlake/acpi/lpit.asl
index 93bce26..9b27c83 100644
--- a/src/soc/intel/cannonlake/acpi/lpit.asl
+++ b/src/soc/intel/cannonlake/acpi/lpit.asl
@@ -64,6 +64,7 @@
    		 */
    		If(Arg2 == 5) {
    			_SB.PCI0.LPCB.EC0.S0IX(1)
+				Sleep(50)
    			/* provide board level s0ix hook */
    			If (CondRefOf (_SB.MS0X)) {
    				_SB.MS0X(1)
@@ -74,6 +75,7 @@
    		 */
    		If(Arg2 == 6) {
    			_SB.PCI0.LPCB.EC0.S0IX(0)
+				Sleep(50)
    			/* provide board level s0ix hook */
    			If (CondRefOf (_SB.MS0X)) {
    				_SB.MS0X(0)