Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44733 )
Change subject: Documentation: Add known bugs of x86_64 code on real hardware ......................................................................
Documentation: Add known bugs of x86_64 code on real hardware
The bugs happen on real hardware or in qemu with KVM enabled. The very same code runs on some real devices and it runs in qemu with KVM disabled.
The bugs are so strange that no root cause could be found yet.
Change-Id: I01050f2e38f92c6b96e3258a5b619aa9ee685acc Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M Documentation/arch/x86/index.md 1 file changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/44733/1
diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md index 11d8a4f..a5406c0 100644 --- a/Documentation/arch/x86/index.md +++ b/Documentation/arch/x86/index.md @@ -65,3 +65,18 @@ * Test how well CAR works with x86_64 and paging * Improve mode switches * Test libgfxinit / VGA Option ROMs / FSP + +## Known bugs on real hardware + +The `x86_64` reference code runs fine in qemu and on some real x86 platforms. +However some issues have been observed and no workaround or explanation could +be found. It either works fine or not at all. Here's a list of known issues: + +* After entering long mode the FPU doesn't work any more, including accessing + MMX register. It works fine before entering long mode. +* Reading from virtual memory where the lower twelve address bits are zero + returns a fixed constant. Writing to that memory location has no effect. + Depeding on the variables stored in heap and stack and where the code + resides, undefined behaviour happens whenever the lower twelve bits are zero. +* Disabling paging in compability mode crashes the CPU. +* Returning from long mode to compability mode crashes the CPU.