[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp: Modify FSP-T code caching parameters

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39625 )

Change subject: soc/intel/xeon_sp: Modify FSP-T code caching parameters
......................................................................

Patch Set 6: Code-Review+2

(1 comment)

https://review.coreboot.org/c/coreboot/+/39625/6/src/soc/intel/xeon_sp/bootb... 
File src/soc/intel/xeon_sp/bootblock/bootblock.c:

https://review.coreboot.org/c/coreboot/+/39625/6/src/soc/intel/xeon_sp/bootb... 
PS6, Line 31: 	.MicrocodeRegionBase = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LOC,
            : 		.MicrocodeRegionLength = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LEN,
            : 		.CodeRegionBase = (UINT32)CACHE_ROM_BASE,
            : 		.CodeRegionLength = (UINT32)CACHE_ROM_SIZE,
Why the casts?