Ken Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38860 )
Change subject: mb/google/hatch: Create palkia variant ......................................................................
Patch Set 13:
(16 comments)
https://review.coreboot.org/c/coreboot/+/38860/2/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/palkia/memory.c:
https://review.coreboot.org/c/coreboot/+/38860/2/src/mainboard/google/hatch/... PS2, Line 87: /* : * For boards with id 0 or unknown, memory straps 3 and 4 are : * incorrectly stuffed in hardware. This is a workaround for these : * boards to override memory strap 3 to 0 and 4 to 1. : */
Palkia did not need this patch . So remove it .
Done
https://review.coreboot.org/c/coreboot/+/38860/2/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/palkia/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/38860/2/src/mainboard/google/hatch/... PS2, Line 9: [PchSerialIoIndexI2C3] = PchSerialIoPci,
Should be disabled
Done
https://review.coreboot.org/c/coreboot/+/38860/2/src/mainboard/google/hatch/... PS2, Line 20: register "usb2_ports[3]" = "USB2_PORT_LONG(OC3)" # Type A : register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type A :
From the schematics, you don't need to set port3. […]
Done
https://review.coreboot.org/c/coreboot/+/38860/2/src/mainboard/google/hatch/... PS2, Line 30: #| GSPI1 | FP MCU |
Remove this.
Done
https://review.coreboot.org/c/coreboot/+/38860/2/src/mainboard/google/hatch/... PS2, Line 30: GSPI1
GSPI1 had removed . Do you jump to […]
Done
https://review.coreboot.org/c/coreboot/+/38860/2/src/mainboard/google/hatch/... PS2, Line 53: .i2c[3] = { : .speed = I2C_SPEED_FAST, : .rise_time_ns = 150, : .fall_time_ns = 150, : },
After verification , the setting can be remove .
Done
https://review.coreboot.org/c/coreboot/+/38860/2/src/mainboard/google/hatch/... PS2, Line 63: .gspi[0] = { : .speed_mhz = 1, : .early_init = 1, : }, : }"
Remove this.
Done
https://review.coreboot.org/c/coreboot/+/38860/2/src/mainboard/google/hatch/... PS2, Line 72: device usb 0.0 on
No right type-c port. Add this: […]
Done
https://review.coreboot.org/c/coreboot/+/38860/2/src/mainboard/google/hatch/... PS2, Line 73: chip drivers/usb/acpi : # No Type-A port : device usb 2.2 off end : end
From Schematics, this should be like this: […]
Done
https://review.coreboot.org/c/coreboot/+/38860/2/src/mainboard/google/hatch/... PS2, Line 77: chip drivers/usb/acpi : # No Type-A Port : device usb 2.3 off end : end
From Schematics, this should be like this: […]
Done
https://review.coreboot.org/c/coreboot/+/38860/2/src/mainboard/google/hatch/... PS2, Line 85: chip drivers/usb/acpi : register "desc" = ""Left Type-A Port"" : register "type" = "UPC_TYPE_A" : register "group" = "ACPI_PLD_GROUP(1, 2)" : device usb 2.4 on end : end : chip drivers/usb/acpi : register "desc" = ""Left Type-A Port"" : register "type" = "UPC_TYPE_A" : register "group" = "ACPI_PLD_GROUP(1, 2)" : device usb 3.4 on end : end
Remove this. I don't see this port from the schematics.
Done
https://review.coreboot.org/c/coreboot/+/38860/2/src/mainboard/google/hatch/... PS2, Line 97: end
Add USB 3 setting as below: […]
Done
https://review.coreboot.org/c/coreboot/+/38860/2/src/mainboard/google/hatch/... PS2, Line 121: register "generic.reset_gpio" = : "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" : register "generic.reset_delay_ms" = "120" : register "generic.reset_off_delay_ms" = "1"
After confirmation , we did not use GPP_D15 . We will remove it .
Done
https://review.coreboot.org/c/coreboot/+/38860/2/src/mainboard/google/hatch/... PS2, Line 137: chip drivers/generic/gpio_keys : register "name" = ""PENH"" : register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" : register "key.wake" = "GPE0_DW0_08" : register "key.wakeup_event_action" = "EV_ACT_ASSERTED" : register "key.dev_name" = ""EJCT"" : register "key.linux_code" = "SW_PEN_INSERTED" : register "key.linux_input_type" = "EV_SW" : register "key.label" = ""pen_eject"" : device generic 0 on end : end
Sorry for the misunderstanding , we do not support pen garage . We can remove it .
Done
https://review.coreboot.org/c/coreboot/+/38860/2/src/mainboard/google/hatch/... PS2, Line 157: register "generic.reset_gpio" = : "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" : register "generic.reset_delay_ms" = "120" : register "generic.reset_off_delay_ms" = "1"
After confirmation , we did not use GPP_D15 . We will remove it .
Done
https://review.coreboot.org/c/coreboot/+/38860/2/src/mainboard/google/hatch/... PS2, Line 206: device pci 1e.3 on : chip drivers/spi/acpi : register "name" = ""CRFP"" : register "hid" = "ACPI_DT_NAMESPACE_HID" : register "uid" = "1" : register "compat_string" = ""google,cros-ec-spi"" : register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A23_IRQ)" : register "wake" = "GPE0_DW0_23" : device spi 1 on end : end # FPMCU : end # GSPI #1
We don't use GSPI1, remove it. ie: […]
Done